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1.发明授权公开(公告)号：US06410431B1
公开(公告)日：2002-06-25
申请号：US09746534
申请日：2000-12-19
IPC分类号： H01L2144
摘要： Through-chip conductors for low inductance chip-to-chip integration and off-chip connections in a semiconductor package is disclosed. A semiconductor device has active devices on the front surface, a first through-chip conductor having first electrical/physical characteristics passing from the front surface of the device to the back surface, a second through-chip conductor having second electrical/physical characteristics passing to the back surface, and an off-chip or chip-to-chip connector electrically connecting the active devices on the front surface to a different level of packaging.
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2.发明授权公开(公告)号：US06222276B1
公开(公告)日：2001-04-24
申请号：US09056277
申请日：1998-04-07
IPC分类号： H01L2352
CPC分类号： H01L23/13 , H01L23/3677 , H01L23/481 , H01L2223/6622 , H01L2224/05567 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/05624 , H01L2224/05647 , H01L2224/05664 , H01L2224/05684 , H01L2224/06181 , H01L2224/16145 , H01L2224/16227 , H01L2224/16265 , H01L2224/1703 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06562 , H01L2225/06565 , H01L2225/06572 , H01L2924/19104 , H01L2924/00014
摘要： Through-chip conductors for low inductance chip-to-chip integration and off-chip connections in a semiconductor package is disclosed. A semiconductor device has active devices on the front surface, a first through-chip conductor having first electrical/physical characteristics passing from the front surface of the device to the back surface, a second through-chip conductor having second electrical/physical characteristics passing to the back surface, and an off-chip or chip-to-chip connector electrically connecting the active devices on the front surface to a different level of packaging.
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公开(公告)号：US06255208B1
公开(公告)日：2001-07-03
申请号：US09236927
申请日：1999-01-25
申请人： William Emmett Bernier , Claude Louis Bertin , Anilkumar Chinuprasad Bhatt , Michael Anthony Gaynes , Erik Leigh Hedberg , Nikhil M. Murdeshwar , Mark Vincent Pierson , William R. Tonti , Paul A. Totta , Joseph John Van Horn , Jerzy Maria Zalesinski
发明人： William Emmett Bernier , Claude Louis Bertin , Anilkumar Chinuprasad Bhatt , Michael Anthony Gaynes , Erik Leigh Hedberg , Nikhil M. Murdeshwar , Mark Vincent Pierson , William R. Tonti , Paul A. Totta , Joseph John Van Horn , Jerzy Maria Zalesinski
IPC分类号： H01L2144
CPC分类号： H01L24/12 , H01L24/11 , H01L24/16 , H01L24/29 , H01L24/83 , H01L2224/05568 , H01L2224/05573 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/1134 , H01L2224/13111 , H01L2224/13116 , H01L2224/13144 , H01L2224/13164 , H01L2224/29101 , H01L2224/29111 , H01L2224/2919 , H01L2224/8319 , H01L2224/838 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0781 , H01L2924/09701 , H01L2924/14 , H01L2924/15747 , H01L2924/30107 , H01L2924/00014 , H01L2224/13099 , H01L2924/00 , H01L2924/3512
摘要： Selective electrical connections between an electronic component and a test substrate are made using an electrical conductive material. The conductive material of the present invention is a dissolvable material, allowing for rework and repair of a wafer at the wafer-level, and retesting at the wafer-level. In addition, the conductive material may also be used in a permanent package, since the conductive material of the present invention provides complete electrical conductivity and connection between the electronic component and the substrate.
摘要翻译： 使用导电材料制成电子部件和测试基板之间的选择性电连接。 本发明的导电材料是可溶解的材料，允许在晶片级对晶片进行返修和修复，并且在晶片级重新测试。 此外，由于本发明的导电材料提供完整的导电性和电子元件与基片之间的连接，导电材料也可用于永久性封装。
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4.发明授权Coaxial wiring within SOI semiconductor, PCB to system for high speed operation and signal quality 失效SOI半导体内同轴布线，PCB到系统高速运行和信号质量公开(公告)号：US06943452B2
公开(公告)日：2005-09-13
申请号：US10103297
申请日：2002-03-21
申请人： Claude Louis Bertin , Gordon Arthur Kelley , Dennis Arthur Schmidt , William Robert Tonti , Jerzy Maria Zalesinski
发明人： Claude Louis Bertin , Gordon Arthur Kelley , Dennis Arthur Schmidt , William Robert Tonti , Jerzy Maria Zalesinski
IPC分类号： H01L21/768 , H01L21/84 , H01L23/66 , H05K1/02 , H05K3/34 , H05K3/46 , H01L23/12 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H05K1/0221 , H01L21/84 , H01L23/66 , H01L2223/6616 , H01L2223/6622 , H01L2223/6627 , H01L2924/0002 , H01L2924/09701 , H01L2924/1903 , H01L2924/3011 , H05K3/3436 , H05K3/3447 , H05K3/4644 , H05K2201/09509 , H05K2201/09518 , H05K2201/09809 , H05K2201/09981 , H05K2201/10356 , H05K2201/10674 , H05K2203/061 , H01L2924/00
摘要： An integrated circuit is provided that contains a coaxial signal line formed at least partially within a silicon-containing substrate. The coaxial signal line comprises an inner conductor having a length, said length axially surrounded by, and insulated from, an outer conductor along said length. A method of preparing such an integrated circuit having said coaxial signal line formed at least partially within a silicon-containing substrate is also disclosed herein.
摘要翻译： 提供一种集成电路，其包含至少部分地形成在含硅衬底内的同轴信号线。 同轴信号线包括内部导体，其具有沿着所述长度的外部导体的长度，所述长度被轴向包围并绝缘。 本文还公开了一种制备具有至少部分地形成在含硅衬底内的所述同轴信号线的集成电路的方法。
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5.发明授权Coaxial wiring within SOI semiconductor, PCB to system for high speed operation and signal quality 失效SOI半导体内同轴布线，PCB到系统高速运行和信号质量公开(公告)号：US06388198B1
公开(公告)日：2002-05-14
申请号：US09265098
申请日：1999-03-09
申请人： Claude Louis Bertin , Gordon Arthur Kelley , Dennis Arthur Schmidt , William Robert Tonti , Jerzy Maria Zalesinski
发明人： Claude Louis Bertin , Gordon Arthur Kelley , Dennis Arthur Schmidt , William Robert Tonti , Jerzy Maria Zalesinski
IPC分类号： H05K109
CPC分类号： H05K1/0221 , H01L21/84 , H01L23/66 , H01L2223/6616 , H01L2223/6622 , H01L2223/6627 , H01L2924/0002 , H01L2924/09701 , H01L2924/1903 , H01L2924/3011 , H05K3/3436 , H05K3/3447 , H05K3/4644 , H05K2201/09509 , H05K2201/09518 , H05K2201/09809 , H05K2201/09981 , H05K2201/10356 , H05K2201/10674 , H05K2203/061 , H01L2924/00
摘要： An integrated circuit that contains a coaxial signal line formed at least partially within a silicon-containing substrate. The coaxial signal line comprises an inner conductor having a length, said length axially surrounded by, and insulated from, an outer conductor along said length. A method of preparing such an integrated circuit having said coaxial signal line formed at least partially within a silicon-containing substrate is also disclosed herein.
摘要翻译： 一种集成电路，其包含至少部分地形成在含硅衬底内的同轴信号线。 同轴信号线包括内导体，其具有沿着所述长度的外导体沿轴向包围并绝缘的长度。 本文还公开了一种制备具有至少部分地形成在含硅衬底内的所述同轴信号线的集成电路的方法。
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6.发明授权Semiconductor stack structures and fabrication sparing methods utilizing programmable spare circuit 失效半导体堆叠结构和利用可编程备用电路的制造备用方法
公开(公告)号：US5798282A
公开(公告)日：1998-08-25
申请号：US429981
申请日：1995-04-27
IPC分类号： H01L21/66 , H01L23/538 , H01L25/065 , H01L25/18 , H01L21/50
CPC分类号： H01L24/49 , G11C29/808 , H01L22/22 , H01L23/5382 , H01L25/0657 , H01L25/18 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/4911 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2225/06551 , H01L2225/06582 , H01L2225/06596 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01033 , H01L2924/01058 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15312 , H01L2924/181 , H01L2924/19107
摘要： Electronic semiconductor structures, and fabrication and sparing methods, each utilize an electrically programmable spare circuit incorporated with a multichip package. The programmable sparing capability in the multichip package is accomplished either with or without the inclusion of a spare chip(s). With a spare memory circuit, individual failed memory cells in the semiconductor chips of a stack can be functionally replaced by memory cells of the spare memory circuit subsequent to encapsulation and burn-in testing. With use of a spare chip, non-volatile sparing can occur subsequent to encapsulation and burn-in testing without physical rewiring of a wire bond connection. Specific details of alternate electronic semiconductor structures, and fabrication and sparing methods therefore, are set forth.
摘要翻译： 电子半导体结构以及制造和备用方法各自使用并入多芯片封装的电可编程备用电路。 多芯片封装中的可编程保护功能可以在有或没有包含备用芯片的情况下完成。 利用备用存储器电路，在封装和老化测试之后，堆叠的半导体芯片中的单个故障存储器单元可以在功能上被备用存储器电路的存储单元替代。 使用备用芯片，在封装和老化测试之后可能会发生非易失性保护，而无需线接合连接的物理重新布线。 因此，提出了替代电子半导体结构的具体细节，以及制造和备用方法。
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公开(公告)号：US5719438A
公开(公告)日：1998-02-17
申请号：US469090
申请日：1995-06-06
申请人： Kenneth Edward Beilstein, Jr. , Claude Louis Bertin , John Edward Cronin , Wayne John Howell , James Marc Leas , David Jacob Perlman
发明人： Kenneth Edward Beilstein, Jr. , Claude Louis Bertin , John Edward Cronin , Wayne John Howell , James Marc Leas , David Jacob Perlman
IPC分类号： H01L21/98 , H01L23/498 , H01L25/065 , H01L25/18 , H01L23/02 , H01L23/04
CPC分类号： H01L25/50 , H01L23/49827 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2224/16145 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/49107 , H01L2224/49109 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2225/06555 , H01L2225/06572 , H01L2225/06582 , H01L2225/06586 , H01L2225/06589 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/01039 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/15312 , H01L2924/1532 , H01L2924/16152 , H01L2924/16195 , H01L2924/30107
摘要： A fabrication method and resultant monolithic electronic module having a separately formed thin-film layer attached to a side surface. The fabrication method includes providing an electronic module composed of stacked integrated circuit chips. A thin-film layer is separately formed on a temporary support which is used to attach the thin-film layer to the electronic module. The disclosed techniques may also be used for attaching an interposer, which may include active circuity, to an electronic module. Specific details of the fabrication method, resulting multichip packages, and various thin-film structures are set forth.
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公开(公告)号：US5702984A
公开(公告)日：1997-12-30
申请号：US749124
申请日：1996-11-14
申请人： Claude Louis Bertin , Wayne John Howell , Erik Leigh Hedberg , Howard Leo Kalter , Gordon Arthur Kelley, Jr.
发明人： Claude Louis Bertin , Wayne John Howell , Erik Leigh Hedberg , Howard Leo Kalter , Gordon Arthur Kelley, Jr.
IPC分类号： H01L25/18 , G11C5/00 , H01L25/00 , H01L25/065 , H01L25/07 , H01L25/10 , H01L25/11 , H01L21/18
CPC分类号： G11C5/06 , G11C11/406 , G11C11/40611 , G11C11/40615 , G11C11/40618 , G11C5/04 , H01L24/49 , H01L25/0657 , H01L2224/05553 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2224/4911 , H01L2224/85207 , H01L2225/0651 , H01L2225/06517 , H01L2225/06551 , H01L2225/06572 , H01L2225/06582 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01058 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/19041 , H01L2924/19107
摘要： An integrated multichip memory module structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the appearance of a single, higher level memory chip. A memory subunit is formed having N memory chips with each memory chip of the subunit having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N.times.M memory devices appears at the module's I/O pins. A preformed electrical interface layer is employed at one end of the memory subunit to electrically interconnect the controlling logic chip with the memory chips comprising the subunit. The controlling logic chip has smaller dimensions than the dimensions of the memory chips comprising the subunit. A lead frame, having an inner opening extending therethrough, is secured to the electrical interface layer and the controlling logic chip is secured to the electrical interface layer so as to reside within the lead frame, thereby producing a dense multichip integrated circuit package. Corresponding fabrication techniques include an approach for facilitating metallization patterning on the side surface of the memory subunit.
摘要翻译： 一种集成多芯片存储器模块结构和制造方法，其中堆叠的半导体存储器芯片由控制逻辑芯片集成，使得以更高级别的存储器芯片的外观定义更强大的存储器架构。 形成具有N个存储器芯片的存储器子单元，该子单元的每个存储器芯片具有M个存储器件。 控制逻辑芯片协调与N个存储器芯片的外部通信，使得在模块的I / O引脚上出现具有NxM存储器件的单个存储器芯片架构。 在存储器子单元的一端采用预先形成的电接口层，以将控制逻辑芯片与包括该子单元的存储器芯片电互连。 控制逻辑芯片的尺寸小于包含子单元的存储器芯片的尺寸。 具有延伸穿过其中的内部开口的引线框固定到电接口层，并且控制逻辑芯片固定到电接口层以便驻留在引线框架内，从而产生致密的多芯片集成电路封装。 相应的制造技术包括促进存储器子单元的侧表面上的金属化图案化的方法。
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9.发明授权Methods and apparatus for burn-in stressing and simultaneous testing of semiconductor device chips in a multichip module 失效多芯片模块中半导体器件芯片的老化应力和同步测试方法和设备
公开(公告)号：US5686843A
公开(公告)日：1997-11-11
申请号：US497126
申请日：1995-06-30
申请人： Kenneth Edward Beilstein, Jr. , Claude Louis Bertin , Dennis Charles Dubois , Wayne John Howell , Gordon Arthur Kelley, Jr. , Christopher Paul Miller , David Jacob Perlman , Gustav Schrottke , Edmund Juris Sprogis , Jody John VanHorn
发明人： Kenneth Edward Beilstein, Jr. , Claude Louis Bertin , Dennis Charles Dubois , Wayne John Howell , Gordon Arthur Kelley, Jr. , Christopher Paul Miller , David Jacob Perlman , Gustav Schrottke , Edmund Juris Sprogis , Jody John VanHorn
CPC分类号： G01R31/2863 , G01R1/0483 , G01R31/2851 , G01R31/2886 , G01R31/2889 , H01L2924/0002
摘要： Methods and apparatus are set forth for burn-in stressing and simultaneous testing of a plurality of semiconductor device chips laminated together in a stack configuration to define a multichip module. Testing is facilitated by connecting temporary interconnect wiring to an access surface of the multichip module. This temporary interconnect wiring electrically interconnects at least some semiconductor device chips within the module. Prior to burn-in stressing and testing, a separate electrical screening step occurs to identify any electrical defect in the connection between the temporary interconnect wiring and the multichip module. If an electrical defect is identified, various techniques for removing or isolating the defect are presented. Thereafter, burn-in stressing and simultaneous testing of the semiconductor chips within the multichip module occurs using the temporary interconnect wiring. Various alignment and test fixtures are described for facilitating this burn-in and simultaneous testing of the semiconductor chips within the multichip module.
摘要翻译： 阐述了以堆叠配置层叠在一起的多个半导体器件芯片的老化应力和同时测试方法和装置，以限定多芯片模块。 通过将临时互连线连接到多芯片模块的访问表面来实现测试。 该临时互连布线使模块内的至少一些半导体器件芯片电互连。 在老化应力和测试之前，会发生单独的电气筛选步骤，以识别临时互连线路和多芯片模块之间的连接中的任何电气缺陷。 如果识别出电气缺陷，则提出了用于去除或隔离缺陷的各种技术。 此后，使用临时互连布线发生多芯片模块内的半导体芯片的老化强度和同时测试。 描述了各种对准和测试夹具，以便于该多芯片模块内的半导体芯片的老化和同时测试。
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10.发明授权Semiconductor chip having chip metal layer and transfer metal layer composed of same metal, and corresponding electronic module 失效具有芯片金属层和由相同金属组成的转移金属层的半导体芯片及相应的电子模块
公开(公告)号：US5644162A
公开(公告)日：1997-07-01
申请号：US660556
申请日：1996-06-10
申请人： Kenneth Edward Beilstein, Jr. , Claude Louis Bertin , Timothy Harrison Daubenspeck , Wayne John Howell
发明人： Kenneth Edward Beilstein, Jr. , Claude Louis Bertin , Timothy Harrison Daubenspeck , Wayne John Howell
IPC分类号： H01L25/18 , H01L21/02 , H01L21/301 , H01L21/3205 , H01L21/822 , H01L21/98 , H01L23/52 , H01L25/065 , H01L25/07 , H01L27/00 , H01L27/04 , H01L23/48
CPC分类号： H01L25/50 , H01L24/24 , H01L25/0657 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2924/14
摘要： A fabrication method including a semiconductor chip kerf clear process and a resulting semiconductor chip and electronic module formed thereby. The fabrication method includes providing a wafer comprising a plurality of integrated circuit chips having kerf regions between them. Chip metallization is present within the kerf regions. A photolithography process is used to protect the wafer exposing only the kerf regions. Next, the wafer is etched, clearing the chip metallization from the kerf regions. The wafer is then diced and the chips are stacked to form a monolithic electronic module. A side surface of the electronic module is processed to expose transfer metals extending thereto, thereby facilitating electrical connection to the chips within the electronic module. Specific details of the fabrication method, resulting integrated circuit chips and monolithic electronic module are set forth.
摘要翻译： 一种制造方法，包括半导体芯片切痕工艺以及由此形成的半导体芯片和电子模块。 制造方法包括提供包括多个集成电路芯片的晶片，其中它们之间具有切口区域。 芯片金属化存在于切口区域内。 使用光刻工艺来保护仅暴露切口区域的晶片。 接下来，蚀刻晶片，从切口区域清除芯片金属化。 然后切割晶片，并且将芯片堆叠以形成单片电子模块。 处理电子模块的侧表面以暴露延伸到其上的转移金属，从而便于与电子模块内的芯片的电连接。 阐述了制造方法的具体细节，所得到的集成电路芯片和单片电子模块。
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