公开(公告)号：US08283982B2

公开(公告)日：2012-10-09

申请号：US12939031

申请日：2010-11-03

Applicant: David Kyong-Sik Chung ,  Afshin Momtaz

Inventor： David Kyong-Sik Chung ,  Afshin Momtaz

IPC: H03F3/04

CPC classification number: H04L25/03878 ,  H04L25/03146

Abstract: An equalization circuit adjusts (e.g., equalizes) an input signal according to the value of one or more adjustment signals (e.g., equalization coefficients) without a multiplication operation. For example, the circuit may add or subtract a value of a coefficient signal to the amplitude of an input signal. Here, whether the coefficient is added or subtracted may depend on the sign of a control signal.

Abstract translation: 均衡电路根据一个或多个调整信号的值（例如，均衡系数）调整（例如，均衡）输入信号而不进行乘法运算。 例如，电路可以将系数信号的值加到或减去输入信号的幅度。 这里，系数是否被相加或取决于控制信号的符号。

公开(公告)号：US07991101B2

公开(公告)日：2011-08-02

申请号：US11705316

申请日：2007-02-12

Applicant: Namik K. Kocaman ,  Afshin Momtaz

Inventor： Namik K. Kocaman ,  Afshin Momtaz

IPC: H04L7/02

CPC classification number: H04L7/033 ,  H04L7/0008

Abstract: Multiple channel synchronized clock generation scheme. A novel approach is presented herein in which synchronized clock signals are generated that can be used in parallel processing of deserialized signals. When a serial input signal is received, it can be deserialized into a plurality of parallel signals, and each of these parallel signals can be processed at a frequency that is lower than the frequency of the serial signal. Overall, the frequency at which all of the parallel signals are processed can be the same or substantially close to the frequency of the serial signal, so that throughput within a communication system is not compromised or undesirably reduced. This novel approach is operable to perform independent adjustment of the operational parameters within an apparatus that is operable to perform multiple channel synchronized clock generation (e.g., phase rotation and/or division of signals within each of the individual channels can be adjusted independently).

Abstract translation: 多通道同步时钟生成方案。 本文提出了一种新颖的方法，其中产生可以并行处理反序列化信号的同步时钟信号。 当串行输入信号被接收时，它可以被反序列化成多个并行信号，并且这些并行信号中的每一个可以以低于串行信号频率的频率进行处理。 总的来说，所有并行信号被处理的频率可以相同或基本上接近串行信号的频率，使得通信系统内的吞吐量不会受到损害或不期望地减少。 这种新颖的方法可操作以对可操作以执行多信道同步时钟生成的装置中的操作参数进行独立调整（例如，可以独立地调整各个信道内的信号的相位旋转和/或除法）。

公开(公告)号：US07973681B2

公开(公告)日：2011-07-05

申请号：US12567841

申请日：2009-09-28

Applicant: Adesh Garg ,  Afshin Momtaz ,  Namik Kocaman ,  Delong Cui

Inventor： Adesh Garg ,  Afshin Momtaz ,  Namik Kocaman ,  Delong Cui

IPC: H03M7/12

CPC classification number: H04L25/0276 ,  H03M5/04 ,  H04L25/0274 ,  H04L25/0282 ,  H04L25/0284

Abstract: A gating logic receives a non-return-to-zero (NRZ) input signal and couples the NRZ input signal as an NRZ output signal when operating in a NRZ mode of operation and converts the NRZ input signal to a return-to-zero (RZ) output signal when operating in a RZ mode of operation. A circuit coupled to the gating logic receives a clock signal and couples the clock signal to the gating logic to convert the NRZ input signal to the RZ output signal in the RZ mode of operation. In the NRZ mode of operation, the circuit decouples the clock signal and places a predetermined signal state at the gating logic to pass through the NRZ input signal as the NRZ output signal. The circuit receives a select signal to select between the NRZ and RZ modes of operation and the NRZ and RZ modes are obtained by controlling the clock signal to the gating logic.

Abstract translation: 门控逻辑接收非归零（NRZ）输入信号，并且在NRZ工作模式下将NRZ输入信号耦合为NRZ输出信号，并将NRZ输入信号转换为零（ RZ）输出信号。 耦合到门控逻辑的电路接收时钟信号并将时钟信号耦合到门控逻辑，以将RZ输入信号转换为RZ工作模式的RZ输出信号。 在NRZ工作模式下，电路解耦时钟信号，并在门控逻辑上放置预定的信号状态，以通过NRZ输入信号作为NRZ输出信号。 电路接收选择信号以在NRZ和RZ工作模式之间进行选择，并通过控制门控逻辑的时钟信号获得NRZ和RZ模式。

公开(公告)号：US07911365B2

公开(公告)日：2011-03-22

申请号：US12656055

申请日：2010-01-14

Applicant: Jun Cao ,  Afshin Momtaz

Inventor： Jun Cao ,  Afshin Momtaz

IPC: H03M1/10

CPC classification number: H03M1/1061 ,  H03M1/362

Abstract: An analog-to-digital converter (ADC) is provided. The ADC includes a reference voltage generator configured to generate reference voltages, an analog to digital converter core configured to receive an input signal and the reference voltages and to generate a digital signal representative of the input signal, the digital signal having a number of bits, and a controller configured to determine a quality of the input signal, and, based on a quality of the input signal, to control the number of bits of the digital signal and values of the reference voltages.

Abstract translation: 提供了一个模拟 - 数字转换器（ADC）。 ADC包括被配置为产生参考电压的参考电压发生器，被配置为接收输入信号和参考电压并且产生代表输入信号的数字信号的模数转换器内核，数字信号具有多个位， 以及控制器，被配置为确定输入信号的质量，并且基于输入信号的质量来控制数字信号的位数和参考电压的值。

公开(公告)号：US20100271120A1

公开(公告)日：2010-10-28

申请号：US12582442

申请日：2009-10-20

Applicant: Afshin Momtaz ,  Namik Kocaman ,  Bharath Raghavan

Inventor： Afshin Momtaz ,  Namik Kocaman ,  Bharath Raghavan

IPC: H03F1/00

CPC classification number: H03F3/45475 ,  H03F3/45183 ,  H03F2203/45686

Abstract: According to one general aspect, an apparatus may include a terminal configured to receive an analog input signal. In various embodiments, the apparatus may also include a multistage amplifier configured to amplify the analog input signal by an amount of gain. In some embodiments, the apparatus may include a distributed threshold adjuster interspersed between the stages of the multistage amplifier configured to adjust the DC voltage of the analog input signal to facilitate a decision by an analog-to-digital converter (ADC). In one embodiment, the apparatus may include the ADC configured to convert the amplified analog input signal to a digital output signal.

Abstract translation: 根据一个一般方面，装置可以包括被配置为接收模拟输入信号的终端。 在各种实施例中，该装置还可以包括多级放大器，其被配置为将模拟输入信号放大一定量的增益。 在一些实施例中，该装置可以包括散布在多级放大器的级之间的分布式阈值调节器，其被配置为调整模拟输入信号的DC电压以便于模数转换器（ADC）的决定。 在一个实施例中，该装置可以包括被配置为将放大的模拟输入信号转换成数字输出信号的ADC。

公开(公告)号：US20100135442A1

公开(公告)日：2010-06-03

申请号：US12314051

申请日：2008-12-03

Applicant: Namik Kemal Kocaman ,  Afshin Momtaz ,  Velu Chellam Pillai ,  Vivek Telang ,  Sundararajan Chidambara ,  Magesh Valliappan

Inventor： Namik Kemal Kocaman ,  Afshin Momtaz ,  Velu Chellam Pillai ,  Vivek Telang ,  Sundararajan Chidambara ,  Magesh Valliappan

IPC: H04L27/06

CPC classification number: H04B17/21 ,  H03F3/195 ,  H03F2200/375 ,  H03F2200/405 ,  H04L25/03019 ,  H04L27/08

Abstract: An apparatus and method is disclosed to compensate for one or more offsets in a communications signal. A communications receiver may carry out an offset adjustment algorithm to compensate for the one or more offsets. An initial search procedure determines one or more signal metric maps for one or more selected offset adjustment corrections from the one or more offset adjustment corrections. The offset adjustment algorithm determines one or more optimal points for one or more selected offset adjustment correction based upon the one or more signal maps. The adaptive offset algorithm adjusts each of the one or more selected offset adjustment corrections to their respective optimal points and/or each of one or more non-selected offset adjustment corrections to a corresponding one of a plurality of possible offset corrections to provide one or more adjusted offset adjustment corrections. A tracking mode procedure optimizes the one or more adjusted offset adjustment corrections.

Abstract translation: 公开了一种用于补偿通信信号中的一个或多个偏移的装置和方法。 通信接收机可以执行偏移调整算法来补偿一个或多个偏移。 初始搜索过程从一个或多个偏移调整校正确定一个或多个所选偏移调整校正的一个或多个信号量度图。 偏移调整算法基于一个或多个信号映射确定一个或多个所选偏移调整校正的一个或多个最优点。 自适应偏移算法将一个或多个所选择的偏移调整校正中的每一个调整到它们各自的最佳点和/或一个或多个未选择的偏移调整校正中的每一个到多个可能的偏移校正中的对应的一个，以提供一个或多个 调整后的偏移调整校正。 跟踪模式过程优化一个或多个经调整的偏移调整校正。

公开(公告)号：US07630466B2

公开(公告)日：2009-12-08

申请号：US11281204

申请日：2005-11-15

Applicant: Afshin Momtaz ,  Rajesh Satapathy ,  Chung-Jue Chen

Inventor： Afshin Momtaz ,  Rajesh Satapathy ,  Chung-Jue Chen

IPC: H04B1/10

CPC classification number: H04L25/03057 ,  H03L7/0814 ,  H04L7/0037 ,  H04L7/033 ,  H04L2025/0349 ,  H04L2025/03617 ,  H04L2025/03662 ,  H04L2025/03687 ,  H04L2025/037

Abstract: A search engine selects initial coefficients for a receive equalizer. The search engine may be incorporated into a communication receiver that includes a decision feedback equalizer and clock and data recovery circuit. Here, the search engine may initialize various adaptation loops that may control the operation of, for example, a decision feedback equalizer, a clock and data recovery circuit and a continuous time filter. The receiver may include an analog-to-digital converter that is used to generate soft decision data for some of the adaptation loops.

Abstract translation: 搜索引擎选择接收均衡器的初始系数。 搜索引擎可以并入到包括判决反馈均衡器和时钟和数据恢复电路的通信接收器中。 这里，搜索引擎可以初始化可以控制例如判决反馈均衡器，时钟和数据恢复电路以及连续时间滤波器的操作的各种适配环路。 接收机可以包括用于产生一些适配环路的软判决数据的模拟 - 数字转换器。

公开(公告)号：US07456690B2

公开(公告)日：2008-11-25

申请号：US11135208

申请日：2005-05-23

Applicant: Namik Kemal Kocaman ,  Afshin Momtaz

Inventor： Namik Kemal Kocaman ,  Afshin Momtaz

IPC: H03G3/10

CPC classification number: H03G3/3052 ,  H03G3/001 ,  H03G3/3036

Abstract: A method and apparatus for an automatic gain control (AGC) loop that utilizes multiple comparators to provide constant bandwidth tracking and step response, as well as fine granularity for decision directed convergence. In one embodiment, an odd number of comparators is used with square-law scaling at the output to achieve constant bandwidth step response for a wide range of input amplitude changes.

Abstract translation: 一种用于自动增益控制（AGC）回路的方法和装置，其利用多个比较器来提供恒定的带宽跟踪和阶跃响应，以及用于决策定向收敛的细粒度。 在一个实施例中，使用奇数比较器，在输出处使用平方律缩放来实现宽范围的输入幅度变化的恒定带宽阶跃响应。

公开(公告)号：US07292101B2

公开(公告)日：2007-11-06

申请号：US11116159

申请日：2005-04-27

Applicant: Namik Kemal Kocaman ,  Afshin Momtaz

Inventor： Namik Kemal Kocaman ,  Afshin Momtaz

IPC: H03F3/45

CPC classification number: H03F3/45183 ,  H03F3/45197 ,  H03F2203/45366 ,  H03F2203/45492 ,  H03F2203/45494 ,  H03F2203/45506 ,  H03F2203/45652 ,  H03F2203/45702 ,  H03F2203/45726 ,  H03G1/0088 ,  H03G3/001

Abstract: A variable gain amplifier including a stage. The stage having a set of switchable differential pairs. The stage providing a gain range to a signal and adjusting a gain of the signal. At least one differential pair in each stage is permanently enabled. The variable gain amplifier may include a plurality of cascaded stages including the stage. In addition, the variable gain amplifier may be adjusted through an interleaved thermometer coding method.

Abstract translation: 一种可变增益放大器，包括一个级。 舞台具有一组可切换的差分对。 该级为信号提供增益范围并调整信号的增益。 每个阶段中至少有一个差分对永久启用。 可变增益放大器可以包括包括该级的多个级联级。 此外，可以通过交错式温度计编码方法来调整可变增益放大器。

公开(公告)号：US07266172B2

公开(公告)日：2007-09-04

申请号：US10797770

申请日：2004-03-10

Applicant: Armond Hairapetian ,  Jun Cao ,  Afshin Momtaz

Inventor： Armond Hairapetian ,  Jun Cao ,  Afshin Momtaz

IPC: H03L7/08 ,  H03L7/089

CPC classification number: H03L7/18 ,  H03L7/089 ,  H03L7/099

Abstract: The present invention relates in general to integrated circuits, and in particular to method and circuitry for implementing an improved phase-locked loop (PLL) in complementary metal-oxide-semiconductor (CMOS)technology using current-controlled CMOS (C3MOS) logic. In an exemplary embodiment, a phase-locked loop includes a phase-frequency detector, a Gm cell block, a low pass filter and a voltage controlled oscillator. These various elements of the phase-locked loop are connected to one another in a fully differential manner, i.e., each element has an input and/or an output each having at least a differential signal. In one embodiment, each of these various elements of the phase-locked loop is implemented using C3MOS logic.

Abstract translation: 本发明一般涉及集成电路，特别涉及用于使用电流控制CMOS（C 3）来实现使用互补金属氧化物半导体（CMOS）技术的改进的锁相环（PLL）的方法和电路 MOS）逻辑。 在示例性实施例中，锁相环包括相位频率检测器，Gm单元块，低通滤波器和压控振荡器。 锁相环的这些各种元件以完全差分的方式相互连接，即每个元件具有至少具有差分信号的输入和/或输出。 在一个实施例中，使用C 3 MOS逻辑来实现锁相环的这些各种元件中的每一个。