公开(公告)号：US06653677B2

公开(公告)日：2003-11-25

申请号：US10066013

申请日：2001-10-22

申请人： Fernando Gonzalez

发明人： Fernando Gonzalez

IPC分类号： H01L27108

CPC分类号： H01L21/8221 ,  H01L21/76254 ,  H01L27/0688

摘要： The invention includes a method of forming a semiconductor construction. A first substrate is provided which comprises silicon-containing structures separated from one another by an insulative material. The silicon-containing structures define an upper surface. A second semiconductor substrate is provided which comprises a monocrystalline material having a damage region therein. The second semiconductor substrate is bonded to the silicon-containing structures of the first substrate at the upper surface. The monocrystalline material is then cleaved along the damage region. The invention also encompasses a semiconductor construction comprising a first substrate having silicon-containing structures separated from one another by an insulative material, and a second substrate comprising a monocrystalline material. The silicon-containing structures of the first substrate define an upper surface, and the monocrystalline material of the second substrate is bonded over the silicon-containing structures at the upper surface.

公开(公告)号：US06653195B1

公开(公告)日：2003-11-25

申请号：US09570095

申请日：2000-05-12

申请人： Fernando Gonzalez ,  Raymond A. Turi ,  Graham R. Wolstenholme ,  Charles L. Ingalls

发明人： Fernando Gonzalez ,  Raymond A. Turi ,  Graham R. Wolstenholme ,  Charles L. Ingalls

IPC分类号： H01L2120

CPC分类号： H01L27/24 ,  H01L27/1021

摘要： A vertically oriented diode for use in delivering current to a multi-state memory element in a memory cell. A vertical diode may be disposed in a diode container extending downwardly from a top of a silicon or oxide layer, and may be formed of a combination of silicon and/or metal layers disposed proximate to inner surfaces of a diode container. A multi-state memory element may be formed of a multi-state material, such as a chalcogenide, above a diode to complete a memory cell.

摘要翻译： 用于将电流传送到存储器单元中的多状态存储器元件的垂直取向的二极管。 垂直二极管可以设置在从硅或氧化物层的顶部向下延伸的二极管容器中，并且可以由靠近二极管容器的内表面设置的硅和/或金属层的组合形成。 多状态存储元件可以由二极管上方的多态材料（例如硫族化物）形成以完成存储单元。

公开(公告)号：US06635552B1

公开(公告)日：2003-10-21

申请号：US09592604

申请日：2000-06-12

申请人： Fernando Gonzalez

发明人： Fernando Gonzalez

IPC分类号： H01L2130

CPC分类号： H01L21/8221 ,  H01L21/76254 ,  H01L27/0688

摘要： The invention includes a method of forming a semiconductor construction. A first substrate is provided which comprises silicon-containing structures separated from one another by an insulative material. The silicon-containing structures define an upper surface. A second semiconductor substrate is provided which comprises a monocrystalline material having a damage region therein. The second semiconductor substrate is bonded to the silicon-containing structures of the first substrate at the upper surface. The monocrystalline material is then cleaved along the damage region. The invention also encompasses a semiconductor construction comprising a first substrate having silicon-containing structures separated from one another by an insulative material, and a second substrate comprising a monocrystalline material. The silicon-containing structures of the first substrate define an upper surface, and the monocrystalline material of the second substrate is bonded over the silicon-containing structures at the upper surface.

摘要翻译： 本发明包括形成半导体结构的方法。 提供了第一衬底，其包括通过绝缘材料彼此分离的含硅结构。 含硅结构限定了上表面。 提供了第二半导体衬底，其包括其中具有损伤区域的单晶材料。 第二半导体衬底在上表面与第一衬底的含硅结构结合。 然后将单晶材料沿损伤区域切割。 本发明还包括半导体结构，其包括具有通过绝缘材料彼此分离的含硅结构的第一衬底和包含单晶材料的第二衬底。 第一衬底的含硅结构限定上表面，并且第二衬底的单晶材料在上表面上结合在含硅结构上。

公开(公告)号：US06624057B2

公开(公告)日：2003-09-23

申请号：US10047633

申请日：2002-01-15

申请人： Fernando Gonzalez

发明人： Fernando Gonzalez

IPC分类号： H01L213205

CPC分类号： H01L29/42376 ,  H01L21/28061 ,  H01L21/28114 ,  H01L28/84

摘要： Methods are disclosed for the fabrication of novel polysilicon structures having increased surface areas to achieve lower resistances after silicidation. The structures are applicable, for example, to semiconductor interconnects, polysilicon gate, and capacitor applications. The inventive method provides additional means of obtaining suitable sheet resistivity and resistances for deep submicron applications. Techniques are disclosed for improving the conductivities of a silicided gate structure, a silicided interconnect structure, and capacitor component structures, each of such are situated on a substrate assembly, such as a semiconductor wafer.

公开(公告)号：US06599817B1

公开(公告)日：2003-07-29

申请号：US10133168

申请日：2002-04-26

申请人： Fernando Gonzalez

发明人： Fernando Gonzalez

IPC分类号： H01L21322

CPC分类号： H01L27/0222 ,  H01L21/3221

摘要： The invention includes an array of devices and a charge pump supported by a semiconductive material substrate. A damage region is under the array, and extends less than or equal to 50% of a distance between the array and the charge pump. The invention also includes a method in which a mask is formed over a monocrystalline silicon substrate. A neutral-conductivity-type dopant is implanted through an opening in the mask and into a section of the substrate to produce a damage region. A first boundary extends around the damage region. The masking layer is removed, and epitaxial silicon is formed over the substrate. An array of devices is formed to be supported by the epitaxial silicon. The array is bounded by a second boundary. The first boundary extends less than or equal to 100 microns beyond the second boundary.

公开(公告)号：US06528834B1

公开(公告)日：2003-03-04

申请号：US09653005

申请日：2000-08-31

申请人： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez

发明人： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez

IPC分类号： H01L27108

CPC分类号： H01L28/91 ,  H01L27/10811 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10888 ,  H01L28/65 ,  Y10S257/905

摘要： Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.

公开(公告)号：US06504756B2

公开(公告)日：2003-01-07

申请号：US09808158

申请日：2001-03-15

申请人： Fernando Gonzalez ,  Francis L. Bensistant

发明人： Fernando Gonzalez ,  Francis L. Bensistant

IPC分类号： G11C1604

CPC分类号： G11C16/0475 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0458 ,  G11C2211/5612 ,  H01L29/66825 ,  H01L29/7887

摘要： A flash memory cell in the form of a transistor capable of storing multi-bit binary data is disclosed. A pair of floating gates are provided beneath a control gate. The control gate is connected to a word line while active doped regions (source and drain regions) are connected to respective digit lines. The floating gates are separately charged and read out by controlling voltages applied to the word line and digit lines. The read out charges are decoded into a multi-bit binary value. One or both of the floating gates has a side insulator which connects through a conductor to an associated active doped region thereby forming a capacitor across the side insulator between the floating gate. This capacitor and active region facilitates operation of the transistor as a flash memory cell. Methods of fabricating the memory cell and operating it are also disclosed.

摘要翻译： 公开了能够存储多位二进制数据的晶体管形式的闪存单元。 一对浮动门设置在控制门下方。 控制栅极连接到字线，而有源掺杂区（源极和漏极区）连接到相应的数字线。 浮动栅极通过控制施加到字线和数字线的电压而被单独充电和读出。 读出的电荷被解码为多位二进制值。 浮动栅极中的一个或两个具有通过导体连接到相关联的有源掺杂区域的侧绝缘体，从而在浮置栅极之间的侧绝缘体上形成电容器。 该电容器和有源区域有助于作为闪存单元的晶体管的操作。 还公开了制造存储器单元并进行操作的方法。

公开(公告)号：US06495900B1

公开(公告)日：2002-12-17

申请号：US08969208

申请日：1997-11-12

申请人： Chandra V. Mouli ,  Fernando Gonzalez

发明人： Chandra V. Mouli ,  Fernando Gonzalez

IPC分类号： H01L2900

CPC分类号： H01L29/66136 ,  H01L21/764 ,  H01L29/4983 ,  H01L29/4991

摘要： Structures and methods are disclosed for insulating a polysilicon gate adjacent to an electrically active region with a silicon base layer. A layer of silicon nitride having a thickness in a range from about 100 Å to about 150 Å is conformally deposited over the polysilicon gate. A layer of silicon dioxide is formed over the layer of silicon nitride on the polysilicon gate. The layer of silicon dioxide is subjected to a spacer etch to form spacers upon the layer of silicon nitride and on lateral sidewalls of the polysilicon gate. A portion of the layer of silicon nitride situated between the polysilicon gate and the spacer is removed by an etching process that is selective to silicon dioxide and to polysilicon. The etch forms a recess defined between the polysilicon gate and each respective spacer. A cover layer is formed to close an opening to the recess so as to enclose a void therein. Alternatively, the etch can be a series of selective etches that extends the recess into the silicon base layer, after which the silicon base layer is implanted so that the recess isolates electrically active areas in the silicon base layer. A void is then enclosed below the opening to the recess within the silicon base layer by a cover layer deposited non-conformally thereover.

摘要翻译： 公开了用于将具有硅基层的与电活性区相邻的多晶硅栅极绝缘的结构和方法。 在多晶硅栅极上共形沉积厚度在大约至大约的范围内的氮化硅层。 在多晶硅栅极上的氮化硅层上形成二氧化硅层。 对二氧化硅层进行间隔蚀刻以在氮化硅层和多晶硅栅极的侧壁上形成间隔物。 通过对二氧化硅和多晶硅有选择性的蚀刻工艺来去除位于多晶硅栅极和间隔物之间​​的氮化硅层的一部分。 蚀刻形成在多晶硅栅极和每个相应间隔物之间​​限定的凹部。 形成覆盖层以闭合到凹部的开口以便在其中包围空隙。 或者，蚀刻可以是将凹槽延伸到硅基层中的一系列选择性蚀刻，然后注入硅基层，使得凹陷隔离硅基层中的电活性区域。 然后，通过在其上非保形地沉积的覆盖层将空隙封闭在硅基底层内的开口下方的凹陷处。

公开(公告)号：US06492228B2

公开(公告)日：2002-12-10

申请号：US09783581

申请日：2001-02-15

申请人： Fernando Gonzalez ,  Francis L Benistant

发明人： Fernando Gonzalez ,  Francis L Benistant

IPC分类号： H01L21336

CPC分类号： G11C16/0475 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0458 ,  G11C2211/5612 ,  H01L29/66825 ,  H01L29/7887

摘要： A flash memory cell in the form of a transistor capable of storing multi-bit binary data is disclosed. A pair of floating gates are provided beneath a control gate. The control gate is connected to a word line while source and drain regions are connected to respective digit lines. The floating gates are separately charged and read out by controlling voltages applied to the word line and digit lines. The read out charges are decoded into a multi-bit binary value. Methods of fabricating the memory cell and operating it are also disclosed.

摘要翻译： 公开了能够存储多位二进制数据的晶体管形式的闪存单元。 一对浮动门设置在控制门下方。 控制栅极连接到字线，而源极和漏极区域连接到相应的数字线。 浮动栅极通过控制施加到字线和数字线的电压而被单独充电和读出。 读出的电荷被解码为多位二进制值。 还公开了制造存储器单元并进行操作的方法。

公开(公告)号：US06489219B1

公开(公告)日：2002-12-03

申请号：US08555801

申请日：1995-11-09

申请人： Fernando Gonzalez ,  Thomas A. Figura ,  J. Brett Rolfson

发明人： Fernando Gonzalez ,  Thomas A. Figura ,  J. Brett Rolfson

IPC分类号： H01L21324

CPC分类号： H01L28/40 ,  H01L21/324 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

摘要： An improved method for alloying a semiconductor substrate upon which wordlines enclosed in spacers have been formed, with the substrate exposed between the wordlines. A thin sealing layer is then deposited over the substrate and the wordlines, the sealing layer helping to maintain the alloy in said substrate. The alloying material employed of the substrate is optionally monatomic hydrogen. Alloying the substrate with monatomic hydrogen may also be used after deposition of a metal layer, or at other process steps as desired.

摘要翻译： 一种用于合金化半导体衬底的改进方法，其上已经形成了封闭在间隔物中的字线，衬底暴露在字线之间。 然后在衬底和字线上沉积薄的密封层，密封层有助于将合金保持在所述衬底中。 所用基板的合金材料可以是单原子氢。 将基底与单原子氢合金也可以在沉积金属层之后使用，或者根据需要在其它工艺步骤中使用。