公开(公告)号：US20070198766A1

公开(公告)日：2007-08-23

申请号：US11676847

申请日：2007-02-20

申请人： Makoto Mizukami ,  Shigeru Kinoshita ,  Shigeyuki Takagi

发明人： Makoto Mizukami ,  Shigeru Kinoshita ,  Shigeyuki Takagi

IPC分类号： G06F12/00

CPC分类号： H01L27/115 ,  G11C11/5628 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory includes: a first memory cell transistor including: a first floating gate electrode provided on and insulated from the substrate; and a first control gate electrode provided on and insulated from the first floating gate electrode; and a second memory cell transistor including: a second floating gate electrode provided on and insulated from the substrate, an upper surface being larger than a lower surface, and the upper surface being lower than an upper surface of the first floating gate electrode; and a second control gate electrode provided on and insulated from the second floating gate electrode.

摘要翻译： 半导体存储器包括：第一存储单元晶体管，包括：设置在基板上并与基板绝缘的第一浮栅; 以及设置在所述第一浮栅上并与所述第一浮栅绝缘的第一控制栅极; 以及第二存储单元晶体管，包括：设置在所述基板上并与所述基板绝缘的第二浮栅，上表面大于下表面，并且所述上表面低于所述第一浮栅电极的上表面; 以及设置在第二浮栅上并与第二浮栅电极绝缘的第二控制栅电极。

公开(公告)号：US20070023781A1

公开(公告)日：2007-02-01

申请号：US11493832

申请日：2006-07-27

申请人： Makoto Mizukami ,  Takashi Shinohe

发明人： Makoto Mizukami ,  Takashi Shinohe

IPC分类号： H01L31/00

CPC分类号： H01L29/872 ,  H01L29/1608 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/8611

摘要： A semiconductor rectifier has a semiconductor layer formed on a substrate, an electric field reduced layer of conductive type contrary to that of the semiconductor layer, which is formed on the semiconductor layer positioned on a bottom portion of a trench formed on a portion of the semiconductor layer, a first electrode connected on the semiconductor layer adjacent to the trench by Schottky junction, a second electrode which is connected on sidewalls of the trench by Schottky junction, electrically conductive with the first electrode and made of a material different from that of the first electrode, and a third electrode formed on the substrate at opposite side of the semiconductor layer.

摘要翻译： 半导体整流器具有形成在基板上的半导体层，与半导体层相反的导电类型的电场降低层形成在位于形成在半导体的一部分上的沟槽的底部上的半导体层上 层，通过肖特基结连接在与沟槽相邻的半导体层上的第一电极，通过肖特基结连接在沟槽的侧壁上的第二电极，与第一电极导电并且由不同于第一电极的材料制成 电极，以及在半导体层的相对侧的基板上形成的第三电极。

公开(公告)号：US08841741B2

公开(公告)日：2014-09-23

申请号：US13226883

申请日：2011-09-07

申请人： Masamu Kamaga ,  Makoto Mizukami ,  Takashi Shinohe

发明人： Masamu Kamaga ,  Makoto Mizukami ,  Takashi Shinohe

IPC分类号： H01L31/102 ,  H01L29/66 ,  H01L29/861 ,  H01L29/06

CPC分类号： H01L29/0615 ,  H01L29/0692 ,  H01L29/6609 ,  H01L29/8613

摘要： A high breakdown voltage diode of the present embodiment includes a first conductive semiconductor substrate, a drift layer formed on the first conductive semiconductor substrate and formed of a first conductive semiconductor, a buffer layer formed on the drift layer and formed of a second conductive semiconductor, a second conductive high concentration semiconductor region formed at an upper portion of the buffer layer, a mesa termination unit formed on an end region of a semiconductor apparatus to relax an electric field of the end region when reverse bias is applied between the semiconductor substrate and the buffer layer, and an electric field relaxation region formed at the mesa termination unit and formed of a second conductive semiconductor.A breakdown voltage of a high breakdown voltage diode, in which a pn junction is provided to a semiconductor layer, is increased, and a process yield is improved.

摘要翻译： 本实施例的高击穿电压二极管包括第一导电半导体衬底，形成在第一导电半导体衬底上并由第一导电半导体形成的漂移层，形成在漂移层上并由第二导电半导体形成的缓冲层， 形成在缓冲层的上部的第二导电性高浓度半导体区域，形成在半导体装置的端部区域上的台面终端单元，用于在半导体基板与半导体基板之间施加反向偏压时使末端区域的电场松弛 缓冲层和形成在台面终端单元处并由第二导电半导体形成的电场弛豫区域。 提供了将pn结提供给半导体层的高击穿电压二极管的击穿电压，并且提高了工艺成品率。

公开(公告)号：US08410545B2

公开(公告)日：2013-04-02

申请号：US12710172

申请日：2010-02-22

申请人： Makoto Mizukami ,  Hideyuki Funaki

发明人： Makoto Mizukami ,  Hideyuki Funaki

IPC分类号： H01L29/66

CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： A semiconductor memory includes a semiconductor substrate, a buried insulating film formed on a part of an upper surface of the semiconductor substrate, and a semiconductor layer formed on another part of the upper surface of the semiconductor substrate. Each of the memory cell transistors comprises a first-conductivity-type source region, a first-conductivity-type drain region, and a first-conductivity-type channel region arranged in the semiconductor layer in the column direction, and a gate portion formed on a side surface of the channel region in the row direction.

摘要翻译： 半导体存储器包括半导体衬底，形成在半导体衬底的上表面的一部分上的埋入绝缘膜和形成在半导体衬底的上表面的另一部分上的半导体层。 每个存储单元晶体管包括在列方向上布置在半导体层中的第一导电类型源极区，第一导电型漏极区和第一导电类型沟道区，以及形成在 沟道区域的行方向的侧面。

公开(公告)号：US20120228631A1

公开(公告)日：2012-09-13

申请号：US13217472

申请日：2011-08-25

申请人： Hiroshi KONO ,  Yukio Nakabayashi ,  Takashi Shinohe ,  Makoto Mizukami

发明人： Hiroshi KONO ,  Yukio Nakabayashi ,  Takashi Shinohe ,  Makoto Mizukami

IPC分类号： H01L29/24 ,  H01L29/78

CPC分类号： H01L29/7802 ,  H01L21/049 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/66068 ,  H01L29/7813

摘要： A semiconductor device of an embodiment includes: a silicon carbide substrate including first and second principal surfaces; a first conductive-type first silicon carbide layer provided on the first principal surface of the silicon carbide substrate; a second conductive-type first silicon carbide region formed on a surface of the first silicon carbide layer; a first conductive-type second silicon carbide region formed on a surface of the first silicon carbide region; a second conductive-type third silicon carbide region formed on the surface of the first silicon carbide region; a gate insulating film continuously formed on the surfaces of the first silicon carbide layer, the first silicon carbide region, and the second silicon carbide region; a first electrode formed of silicon carbide formed on the gate insulating film; a second electrode formed on the first electrode; an interlayer insulating film for covering the first and second electrodes; a third electrode electrically connected to the second silicon carbide region and the third silicon carbide region; and a fourth electrode formed on the second principal surface of the silicon carbide substrate.

摘要翻译： 实施例的半导体器件包括：碳化硅衬底，其包括第一和第二主表面; 设置在碳化硅衬底的第一主表面上的第一导电型第一碳化硅层; 形成在所述第一碳化硅层的表面上的第二导电型第一碳化硅区; 形成在所述第一碳化硅区域的表面上的第一导电型第二碳化硅区域; 形成在所述第一碳化硅区域的表面上的第二导电型第三碳化硅区域; 连续形成在所述第一碳化硅层，所述第一碳化硅区域和所述第二碳化硅区域的表面上的栅极绝缘膜; 形成在所述栅极绝缘膜上的由碳化硅形成的第一电极; 形成在第一电极上的第二电极; 用于覆盖第一和第二电极的层间绝缘膜; 电连接到第二碳化硅区域和第三碳化硅区域的第三电极; 以及形成在碳化硅衬底的第二主表面上的第四电极。

公开(公告)号：US08227811B2

公开(公告)日：2012-07-24

申请号：US13036940

申请日：2011-02-28

申请人： Makoto Mizukami ,  Johji Nishio

发明人： Makoto Mizukami ,  Johji Nishio

IPC分类号： H01L31/0312

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/1608

摘要： A wide bandgap semiconductor rectifying device of an embodiment includes a first-conductive-type wide bandgap semiconductor substrate and a first-conductive-type semiconductor layer that has an impurity concentration lower than that of the substrate. The device also includes a first-conductive-type first semiconductor region, and a second-conductive-type second semiconductor region that is formed between the first regions. The device also includes second-conductive-type third semiconductor regions in which at least part of the third regions are connected to the second wide bandgap semiconductor region, the third regions being formed between the first regions, the third regions having a width narrower than that of the second region. The device also includes a first electrode and a second electrode. In the device, a direction in which a longitudinal direction of the third regions are projected onto a (0001) plane of the layer has an angle of 90±30 degrees with respect to a direction of the layer. A gap between the third regions is not lower than 2d×tan 18°, where d is a thickness of the layer.

摘要翻译： 实施例的宽带隙半导体整流装置包括第一导电型宽带隙半导体衬底和杂质浓度低于衬底的杂质浓度的第一导电型半导体层。 该器件还包括形成在第一区域之间的第一导电型第一半导体区域和第二导电型第二半导体区域。 该器件还包括第二导电类型的第三半导体区域，其中至少一部分第三区域连接到第二宽带隙半导体区域，第三区域形成在第一区域之间，第三区域宽度窄于第一区域。 的第二个地区。 该装置还包括第一电极和第二电极。 在该装置中，第三区域的纵向方向投影到层的（0001）平面上的方向相对于层的<11-20>方向具有90±30度的角度。 第三区域之间的间隙不低于2d×tan 18°，其中d是层的厚度。

公开(公告)号：US20120056196A1

公开(公告)日：2012-03-08

申请号：US13034297

申请日：2011-02-24

申请人： Chiharu Ota ,  Takashi Shinohe ,  Makoto Mizukami ,  Johji Nishio

发明人： Chiharu Ota ,  Takashi Shinohe ,  Makoto Mizukami ,  Johji Nishio

IPC分类号： H01L29/12 ,  H01L21/20

CPC分类号： H01L29/1608 ,  H01L21/02529 ,  H01L21/26513 ,  H01L29/47 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/861 ,  H01L29/872

摘要： A semiconductor device according to an embodiment includes a first-conductive-type semiconductor substrate; a first-conductive-type first semiconductor layer formed on the semiconductor substrate, and having an impurity concentration lower than that of the semiconductor substrate; a second-conductive-type second semiconductor layer epitaxially formed on the first semiconductor layer; and a second-conductive-type third semiconductor layer epitaxially formed on the second semiconductor layer, and having an impurity concentration higher than that of the second semiconductor layer. The semiconductor device also includes a recess formed in the third semiconductor layer, and at least a corner portion of a side face and a bottom surface is located in the second semiconductor layer. The semiconductor device also includes a first electrode in contact with the third semiconductor layer; a second electrode connected to the first electrode while being in contact with the second semiconductor layer at the bottom surface of the recess; and a third electrode in contact with a lower surface of the semiconductor substrate.

摘要翻译： 根据实施例的半导体器件包括第一导电型半导体衬底; 形成在半导体衬底上的第一导电型第一半导体层，其杂质浓度低于半导体衬底的杂质浓度; 外延形成在第一半导体层上的第二导电型第二半导体层; 以及外延形成在所述第二半导体层上，并且具有比所述第二半导体层的杂质浓度高的杂质浓度的第二导电型第三半导体层。 半导体器件还包括形成在第三半导体层中的凹部，并且至少侧面和底面的角部位于第二半导体层中。 半导体器件还包括与第三半导体层接触的第一电极; 第二电极，其与所述第一电极连接，同时在所述凹部的底表面处与所述第二半导体层接触; 以及与半导体衬底的下表面接触的第三电极。

公开(公告)号：US20120056195A1

公开(公告)日：2012-03-08

申请号：US13034264

申请日：2011-02-24

申请人： Hiroshi Kono ,  Takashi Shinohe ,  Chiharu Ota ,  Makoto Mizukami ,  Takuma Suzuki ,  Johji Nishio

发明人： Hiroshi Kono ,  Takashi Shinohe ,  Chiharu Ota ,  Makoto Mizukami ,  Takuma Suzuki ,  Johji Nishio

IPC分类号： H01L29/161

CPC分类号： H01L29/7395 ,  H01L29/1033 ,  H01L29/66333

摘要： One embodiment of a semiconductor device includes: a silicon carbide substrate including first and second principal surfaces; a first-conductive-type silicon carbide layer on the first principal surface; a second-conductive-type first silicon carbide region at a surface of the first silicon carbide layer; a first-conductive-type second silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type third silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type fourth silicon carbide region formed between the first silicon carbide region and the second silicon carbide region, and having an impurity concentration higher than that of the first silicon carbide region; a gate insulator; a gate electrode formed on the gate insulator; an inter-layer insulator; a first electrode connected to the second silicon carbide region and the third silicon carbide region; and a second electrode on the second principal surface.

摘要翻译： 半导体器件的一个实施例包括：包含第一和第二主表面的碳化硅衬底; 第一主表面上的第一导电型碳化硅层; 在所述第一碳化硅层的表面处的第二导电型第一碳化硅区域; 在第一碳化硅区域的表面处的第一导电型第二碳化硅区域; 在第一碳化硅区域的表面处的第二导电型第三碳化硅区域; 在第一碳化硅区域和第二碳化硅区域之间形成的杂质浓度高于第一碳化硅区域的第二导电型第四碳化硅区域; 栅极绝缘体; 形成在栅绝缘体上的栅电极; 层间绝缘体; 连接到所述第二碳化硅区域和所述第三碳化硅区域的第一电极; 和在第二主表面上的第二电极。

公开(公告)号：US20110059597A1

公开(公告)日：2011-03-10

申请号：US12716403

申请日：2010-03-03

申请人： Johji Nishio ,  Chiharu Ota ,  Takuma Suzuki ,  Hiroshi Kono ,  Makoto Mizukami ,  Takashi Shinohe

发明人： Johji Nishio ,  Chiharu Ota ,  Takuma Suzuki ,  Hiroshi Kono ,  Makoto Mizukami ,  Takashi Shinohe

IPC分类号： H01L21/20

CPC分类号： H01L29/7802 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02658 ,  H01L21/0495 ,  H01L21/30604 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66143 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device capable of realizing a high yield of a large-scale semiconductor device even when a silicon carbide semiconductor including a defect is used is provided. The method of manufacturing a semiconductor device includes: a step of epitaxially growing a silicon carbide semiconductor layer on a silicon carbide semiconductor substrate; a step of polishing a surface of the silicon carbide semiconductor layer; a step of ion-implanting impurities into the silicon carbide semiconductor layer after the step of polishing; a step of performing heat treatment to activate the impurities; a step of forming a first thermal oxide film on the surface of the silicon carbide semiconductor layer after the step of performing heat treatment; a step of chemically removing the first thermal oxide film; and a step of forming an electrode layer on the silicon carbide semiconductor film.

摘要翻译： 提供了即使当使用包括缺陷的碳化硅半导体时也能够实现大规模半导体器件的高产率的半导体器件的制造方法。 制造半导体器件的方法包括：在碳化硅半导体衬底上外延生长碳化硅半导体层的步骤; 抛光所述碳化硅半导体层的表面的步骤; 在抛光步骤之后将杂质离子注入到碳化硅半导体层中的步骤; 进行热处理以活化杂质的步骤; 在进行热处理的步骤之后，在碳化硅半导体层的表面上形成第一热氧化膜的工序; 化学去除第一热氧化膜的步骤; 以及在所述碳化硅半导体膜上形成电极层的步骤。

公开(公告)号：US20090020744A1

公开(公告)日：2009-01-22

申请号：US12163145

申请日：2008-06-27

申请人： Makoto Mizukami ,  Takeshi Kamigaichi

发明人： Makoto Mizukami ,  Takeshi Kamigaichi

IPC分类号： H01L45/00 ,  H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/5283 ,  H01L21/0217 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/24 ,  H01L45/06 ,  H01L2924/0002 ,  Y10T156/1057 ,  H01L2924/00

摘要： A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.

摘要翻译： 根据本发明实施例的叠层多层结构包括：堆叠层部分，包括多个导电层和多个绝缘层，所述多个绝缘层与所述多个导电层的每个层交替叠层，一个 所述多个绝缘层是所述多个导电层和所述多个绝缘层中的最上层; 和多个触点，所述多个触点的每个触点由所述最顶层形成，并且所述多个触点的每个触点与所述多个导电层的相应导电层接触，所述多个触点的每一个的侧表面 的触点经由绝缘膜与所述多个导电层绝缘。