公开(公告)号：US20170040110A1

公开(公告)日：2017-02-09

申请号：US14818342

申请日：2015-08-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Min-hwa CHI

IPC: H01G4/012 ,  H01G4/30

CPC classification number: H01G4/012 ,  H01G4/306 ,  H01G4/33 ,  H01L23/5222 ,  H01L28/82 ,  H01L28/90

Abstract: Capacitor structures having first electrodes at least partially embedded within a second electrode, and fabrication methods are presented. The methods include, for instance: providing the first electrodes at least partially within an insulator layer, the first electrodes comprising exposed portions; covering exposed portions of the first electrodes with a dielectric material; and forming the second electrode at least partially around the dielectric covered portions of the first electrodes, the second electrode being physically separated from the first electrodes by the dielectric material. In one embodiment, a method further includes exposing further portions of the first electrodes; and providing a contact structure in electrical contact with the further exposed portions of the first electrodes. In another embodiment, some of the first electrodes are aligned substantially parallel to a first direction and other of the first electrodes are aligned substantially parallel to a second direction, the first and second directions being different directions.

Abstract translation: 具有至少部分地嵌入在第二电极内的第一电极的电容器结构以及制造方法。 所述方法包括例如：至少部分地在绝缘体层内提供第一电极，第一电极包括暴露部分; 用介电材料覆盖第一电极的暴露部分; 以及至少部分地围绕所述第一电极的所述电介质覆盖部分形成所述第二电极，所述第二电极通过所述电介质材料与所述第一电极物理分离。 在一个实施例中，一种方法还包括暴露第一电极的另外部分; 以及提供与第一电极的另外的暴露部分电接触的接触结构。 在另一个实施例中，一些第一电极基本上平行于第一方向排列，而另一些第一电极基本上平行于第二方向排列，第一和第二方向是不同的方向。

公开(公告)号：US20160322384A1

公开(公告)日：2016-11-03

申请号：US14700748

申请日：2015-04-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Bingwu LIU ,  Xusheng WU

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/73 ,  H01L29/08 ,  H01L21/84 ,  H01L21/02

CPC classification number: H01L29/0684 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/0623 ,  H01L27/1207 ,  H01L29/0847 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/66568 ,  H01L29/732 ,  H01L29/7371 ,  H01L29/78

Abstract: A method can include epitaxially growing epitaxial growth material within a logic region of a semiconductor structure. A method can include performing simultaneously with the growing epitaxial growth within an analog region of the semiconductor structure. A method can include performing epitaxial growth to form an epitaxial growth formation that defines an electrode of an analog device within an analog region of the semiconductor structure, wherein the performing includes using a first surface and a second surface as seed surfaces.

Abstract translation: 一种方法可以包括在半导体结构的逻辑区域内外延生长外延生长材料。 一种方法可以包括与半导体结构的模拟区域内的增长的外延生长同时执行。 一种方法可以包括进行外延生长以形成限定半导体结构的模拟区域内的模拟器件的电极的外延生长结构，其中执行包括使用第一表面和第二表面作为晶种表面。

公开(公告)号：US20160233091A1

公开(公告)日：2016-08-11

申请号：US14616226

申请日：2015-02-06

Applicant: GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hui ZANG ,  Balasubramanian PRANATHARTHIHARAN

IPC: H01L21/283 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L21/76897 ,  H01L29/66545

Abstract: Semiconductor devices and methods for forming the devices with middle of line capacitance reduction in self-aligned contact process flow are provided. One method includes, for instance: obtaining a wafer with at least one source, at least one drain, and at least one sacrificial gate; forming a first contact region over the at least one source and a second contact region over the at least one drain; removing the at least one sacrificial gate; forming at least one gate; and forming at least one small contact over the first contact region and the second contact region. An intermediate semiconductor device is also disclosed.

Abstract translation: 提供了用于形成具有自对准接触工艺流程中线路电容减小的器件的半导体器件和方法。 一种方法包括，例如：获得具有至少一个源，至少一个漏极和至少一个牺牲栅极的晶片; 在所述至少一个源极上形成第一接触区域，以及在所述至少一个漏极上形成第二接触区域; 去除所述至少一个牺牲栅极; 形成至少一个栅极; 以及在所述第一接触区域和所述第二接触区域上形成至少一个小接触。 还公开了一种中间半导体器件。

公开(公告)号：US20160225848A1

公开(公告)日：2016-08-04

申请号：US14609653

申请日：2015-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Bingwu LIU

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L29/10 ,  H01L21/3105

CPC classification number: H01L29/0649 ,  H01L21/02164 ,  H01L21/28017 ,  H01L21/28238 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823481 ,  H01L29/1079 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a SDB including a protective layer or bilayer and the resulting device are provided. Embodiments include forming a SDB of oxide in a Si substrate; forming a nitride layer over the Si substrate; forming a photoresist over the SDB and a portion of the nitride layer; removing the nitride layer on opposite sides of the photoresist down to the Si substrate, leaving a portion of the nitride layer only under the photoresist; forming a gate above the SBD and the portion of the nitride layer.

Abstract translation: 提供了形成包括保护层或双层的SDB的方法和所得到的器件。 实施例包括在Si衬底中形成氧化物的SDB; 在Si衬底上形成氮化物层; 在所述SDB和所述氮化物层的一部分上形成光致抗蚀剂; 将光致抗蚀剂的相对侧上的氮化物层去除到Si衬底，留下一部分氮化物层仅在光致抗蚀剂下面; 在SBD上方形成栅极和氮化物层的部分。

公开(公告)号：US20210066464A1

公开(公告)日：2021-03-04

申请号：US17097419

申请日：2020-11-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui ZANG ,  Ruilong XIE ,  Jae Gon LEE

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/51 ,  H01L29/78 ,  H01L21/768 ,  H01L29/66 ,  H01L23/528 ,  H01L23/522

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a scaled gate contact and source/drain cap and methods of manufacture. The structure includes: a gate structure comprising an active region; source and drain contacts adjacent to the gate structure; a capping material over the source and drain contacts; a gate contact formed directly above the active region of the gate structure and over the capping material; a U-shape dielectric material around the gate contact, above the source and drain contacts; and a contact in direct electrical contact to the source and drain contacts.

公开(公告)号：US20200176324A1

公开(公告)日：2020-06-04

申请号：US16204482

申请日：2018-11-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui ZANG ,  Ruilong XIE

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417 ,  H01L21/311

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures; source and drain regions adjacent to respective gate structures of the plurality of gate structures; metallization features contacting selected source and drain regions; and recessed metallization features contacting other selected source and drain regions.

公开(公告)号：US20200161136A1

公开(公告)日：2020-05-21

申请号：US16193960

申请日：2018-11-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui SHU ,  Hui ZANG

IPC: H01L21/28 ,  H01L23/535 ,  H01L27/088 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8234

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The structure includes: a plurality of gate structures comprising a gate cap, sidewall spacers and source and drain regions; source and drain metallization features extending to the source and drain regions; and a liner extending along an upper portion of the sidewall spacers of at least one of the plurality of gate structures.

公开(公告)号：US20200144365A1

公开(公告)日：2020-05-07

申请号：US16180486

申请日：2018-11-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： George R. MULFINGER ,  Timothy J. MCARDLE ,  Judson R. HOLT ,  Steffen A. SICHLER ,  Ömür I. AYDIN ,  Wei HONG ,  Yi QI ,  Hui ZANG ,  Liu JIANG

IPC: H01L29/08 ,  H01L21/8238 ,  H01L29/06 ,  H01L21/28 ,  H01L29/423

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to faceted epitaxial source/drain regions and methods of manufacture. The structure includes: a gate structure over a substrate; an L-shaped sidewall spacer located on sidewalls of the gate structure and extending over the substrate adjacent to the gate structure; and faceted diffusion regions on the substrate, adjacent to the L-shaped sidewall spacer.

公开(公告)号：US20200066879A1

公开(公告)日：2020-02-27

申请号：US16108753

申请日：2018-08-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui ZANG ,  Guowei XU

IPC: H01L29/66 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/78 ,  H01L21/8234

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to replacement metal gate structures with reduced shorting and uniform chamfering, and methods of manufacture. The structure includes: a long channel device composed of a conductive gate material with a capping layer over the conductive gate material and extending to sides of the conductive gate material; and a short channel device composed of the conductive gate material and the capping layer over the conductive gate material.

公开(公告)号：US20200066593A1

公开(公告)日：2020-02-27

申请号：US16109258

申请日：2018-08-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tek Po Rinus LEE ,  Annie LEVESQUE ,  Qun GAO ,  Hui ZANG ,  Rishikesh KRISHNAN ,  Bharat KRISHNAN ,  Curtis DURFEE

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L23/532 ,  H01L23/535 ,  H01L21/02 ,  H01L29/40

Abstract: A device including a triple-layer EPI stack including SiGe, Ge, and Si, respectively, with Ga confined therein, and method of production thereof. Embodiments include an EPI stack including a SiGe layer, a Ge layer, and a Si layer over a plurality of fins, the EPI stack positioned between and over a portion of sidewall spacers, wherein the Si layer is a top layer capping the Ge layer, and wherein the Ge layer is a middle layer capping the SiGe layer underneath; and a Ga layer in a portion of the Ge layer between the SiGe layer and the Si layer.