公开(公告)号：US09472642B2

公开(公告)日：2016-10-18

申请号：US14693978

申请日：2015-04-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Ralf Richter ,  Peter Javorka

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/283 ,  H01L29/78 ,  H01L29/06 ,  H01L29/45

CPC classification number: H01L29/665 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0629 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/45 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

Abstract: The present disclosure provides in one aspect for a semiconductor device structure which may be formed by providing source/drain regions within a semiconductor substrate in alignment with a gate structure formed over the semiconductor substrate, wherein the gate structure has a gate electrode structure, a first sidewall spacer and a second sidewall spacer, the first sidewall spacer covering sidewall surfaces of the gate electrode structure and the sidewall spacer being formed on the first sidewall spacer. Furthermore, forming the semiconductor device structure may include removing the second sidewall spacer so as to expose the first sidewall spacer, forming a third sidewall spacer on a portion of the first sidewall spacer such that the first sidewall spacer is partially exposed, and forming silicide regions in alignment with the third sidewall spacer in the source/drain regions.

Abstract translation: 本公开在一个方面中提供了半导体器件结构，其可以通过在半导体衬底内提供与在半导体衬底上形成的栅极结构对准的源极/漏极区域形成，其中栅极结构具有栅电极结构，第一 侧壁间隔件和第二侧壁间隔件，所述第一侧壁间隔物覆盖所述栅极电极结构和所述侧壁间隔物的侧壁表面，所述侧壁间隔件形成在所述第一侧壁间隔物上。 此外，形成半导体器件结构可以包括去除第二侧壁间隔物以暴露第一侧壁间隔物，在第一侧壁间隔物的一部分上形成第三侧壁间隔物，使得第一侧壁间隔物部分地暴露，并且形成硅化物区域 与源极/漏极区域中的第三侧壁间隔物对准。

公开(公告)号：US09343374B1

公开(公告)日：2016-05-17

申请号：US14527207

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Peter Javorka ,  Stefan Flachowsky ,  Ralf Richter

IPC: H01L21/336 ,  H01L21/3205 ,  H01L21/4763 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L21/823864 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

Abstract: Forming a poly-Si device including pulling back spacers prior to silicidation and the resulting device are provided. Embodiments include forming two poly-Si gate stacks on an upper surface of a substrate; forming a hardmask over the second poly-Si gate stack; forming eSiGe with a silicon cap at opposite sides of the first poly-Si gate stack; removing the hardmask; forming nitride spacers at opposite sides of each of the poly-Si gate stacks; forming deep source/drain regions at opposite sides of the second poly-Si gate stack; forming a wet gap fill layer around each of the poly-Si gate stacks to a thickness less than the poly-Si gate stack height from the substrate's upper surface; removing an upper portion of the nitride spacers down to the height of the wet gap fill layer followed by removing the wet gap fill layer; and performing silicidation of the deep source/drain regions and the silicon cap.

Abstract translation: 形成包括在硅化之前拉回间隔物的多晶硅器件，并提供所得到的器件。 实施例包括在基板的上表面上形成两个多晶硅栅叠层; 在第二多晶硅栅叠层上形成硬掩模; 在所述第一多晶硅栅叠层的相对侧用硅帽形成eSiGe; 移除硬掩模; 在每个多晶硅栅极堆叠的相对侧形成氮化物间隔物; 在第二多晶硅栅叠层的相对侧形成深源极/漏极区; 在每个多晶硅栅极堆叠周围形成厚度小于距离基板的上表面的多晶硅栅叠层高度的厚度的填充层; 将氮化物间隔物的上部分除去湿间隙填充层的高度，然后除去湿间隙填充层; 并执行深源极/漏极区和硅帽的硅化。

公开(公告)号：US09324868B2

公开(公告)日：2016-04-26

申请号：US14463057

申请日：2014-08-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Ruby Yan ,  Ralf Richter ,  Jan Hoentschel ,  Hans-Jurgen Thees

IPC: H01L21/00 ,  H01L21/84 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L21/306 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L29/7853 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/02639 ,  H01L21/30608 ,  H01L21/76224 ,  H01L21/76283 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7855

Abstract: FinFET devices with epitaxially grown fins and methods for fabricating them are provided. Embodiments include forming at least two shallow trench isolation (STI) regions, filled with dielectric material, adjacent to but separate from each other in a silicon substrate; epitaxially growing a silicon-based layer between each adjacent pair of STI regions to form a fin with a non-rectangular cross-section extending from each STI region to each adjacent STI region; forming a gate oxide over and perpendicular to each fin; and forming a gate electrode over the gate oxide to form a FinFET.

Abstract translation: 提供具有外延生长翅片的FinFET器件及其制造方法。 实施例包括在硅衬底中相邻但彼此分开形成填充有电介质材料的至少两个浅沟槽隔离（STI）区域; 在每个相邻的一对STI区域之间外延生长硅基层以形成具有从每个STI区域延伸到每个相邻STI区域的非矩形横截面的翅片; 在每个翅片上形成栅极氧化物并垂直于每个鳍片; 以及在所述栅极氧化物上形成栅电极以形成FinFET。

公开(公告)号：US09224655B2

公开(公告)日：2015-12-29

申请号：US13792540

申请日：2013-03-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Ralf Richter ,  Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L21/311 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/66545

Abstract: One illustrative method disclosed herein includes the steps of forming a masking layer that covers a P-type transistor and exposes at least a gate cap layer of an N-type transistor, performing a first etching process through the masking layer to remove a portion of the gate cap of the N-type transistor so as to thereby define a reduced thickness gate cap layer for the N-type transistor, removing the masking layer, and performing a common second etching process on the P-type transistor and the N-type transistor that removes a gate cap layer of the P-type transistor and the reduced thickness gate cap of the N-type transistor.

Abstract translation: 本文公开的一种说明性方法包括以下步骤：形成覆盖P型晶体管并暴露N型晶体管的至少栅极帽层的掩模层，通过掩模层执行第一蚀刻工艺以去除部分 N型晶体管的栅极帽，从而限定了用于N型晶体管的减小厚度的栅极盖层，去除掩模层，并对P型晶体管和N型晶体管执行公共的第二蚀刻工艺 其去除了N型晶体管的P型晶体管的栅极盖层和减小厚度的栅极盖。

公开(公告)号：US09012956B2

公开(公告)日：2015-04-21

申请号：US13783517

申请日：2013-03-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Ralf Richter ,  Jan Hoentschel

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L21/823418 ,  H01L21/28518 ,  H01L21/823412 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/66431 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

Abstract: When forming sophisticated P-channel transistors, a semiconductor alloy layer is formed on the surface of the semiconductor layer including the transistor active region. When a metal silicide layer is formed contiguous to this semiconductor alloy layer, an agglomeration of the metal silicide layer into isolated clusters is observed. In order to solve this problem, the present invention proposes a method and a semiconductor device wherein the portion of the semiconductor alloy layer lying on the source and drain regions of the transistor is removed before formation of the metal silicide layer is performed. In this manner, the metal silicide layer is formed so as to be contiguous to the semiconductor layer, and not to the semiconductor alloy layer.

Abstract translation: 当形成复杂的P沟道晶体管时，在包括晶体管有源区的半导体层的表面上形成半导体合金层。 当与该半导体合金层邻接形成金属硅化物层时，观察到金属硅化物层与分离的团簇的聚集。 为了解决这个问题，本发明提出一种方法和半导体器件，其中在形成金属硅化物层之前去除位于晶体管的源极和漏极区域上的半导体合金层的部分。 以这种方式，金属硅化物层形成为与半导体层邻接，而不形成为半导体合金层。

公开(公告)号：US20150076618A1

公开(公告)日：2015-03-19

申请号：US14031361

申请日：2013-09-19

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ran Yan ,  Nicolas Sassiat ,  Ralf Richter ,  Jan Hoentschel

IPC: H01L29/423 ,  H01L29/10 ,  H01L29/40

CPC classification number: H01L29/42376 ,  H01L29/1037 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854

Abstract: Methods and apparatus are provided for an integrated circuit. The method includes forming a corrugation mask on a substrate, and forming a channel corrugation on the substrate. The corrugation mask is removed from the substrate, and a gate insulator is formed overlying the channel corrugation on the substrate. A gate is formed overlying the channel gate insulator.

Abstract translation: 为集成电路提供了方法和装置。 该方法包括在衬底上形成波纹掩模，并在衬底上形成通道波纹。 将波纹掩模从基板上移除，并且在衬底上形成覆盖通道波纹的栅极绝缘体。 栅极形成在通道栅极绝缘体上方。

公开(公告)号：US08951877B2

公开(公告)日：2015-02-10

申请号：US13799741

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicolas Sassiat ,  Carsten Grass ,  Jan Hoentschel ,  Ran Yan ,  Ralf Richter

IPC: H01L21/336 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78642 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/6675

Abstract: When forming cavities in active regions of semiconductor devices in order to incorporate a strain-inducing semiconductor material, an improved shape of the cavities may be achieved by using an amorphization process and a heat treatment so as to selectively modify the etch behavior of exposed portions of the active regions and to adjust the shape of the amorphous regions. In this manner, the basic configuration of the cavities may be adjusted with a high degree of flexibility. Consequently, the efficiency of the strain-inducing technique may be improved.

Abstract translation: 当在半导体器件的有源区域中形成空腔以引入应变诱导半导体材料时，可以通过使用非晶化过程和热处理来实现空腔的改进形状，以便选择性地改变暴露部分的蚀刻行为 活性区域并调整非晶区域的形状。 以这种方式，可以以高度的灵活性来调节空腔的基本构造。 因此，可以提高应变诱导技术的效率。

公开(公告)号：US20140357042A1

公开(公告)日：2014-12-04

申请号：US13907362

申请日：2013-05-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ralf Richter ,  Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/266

CPC classification number: H01L29/6653 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/28008 ,  H01L21/823864 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/6659 ,  H01L29/7833

Abstract: A known problem when manufacturing transistors is the stress undesirably introduced by the spacers into the transistor channel region. In order to solve this problem, the present invention proposes an ion implantation aimed at relaxing the stress of the spacer materials. The relax implantation is performed after the spacer has been completely formed. The relax implantation may be performed after a silicidation process or after an implantation step in the source and drain regions followed by an activation annealing and before performing the silicidation process.

Abstract translation: 制造晶体管时的已知问题是由间隔物不期望地引入晶体管沟道区域的应力。 为了解决这个问题，本发明提出了一种旨在缓和间隔物材料的应力的离子注入。 在间隔件已经完全形成之后进行松弛植入。 松弛植入可以在硅化处理之后或在源极和漏极区域中的注入步骤之后进行激活退火并且在进行硅化处理之前进行。

公开(公告)号：US08877582B2

公开(公告)日：2014-11-04

申请号：US13771294

申请日：2013-02-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Peter Javorka ,  Stefan Flachowsky ,  Nicolas Sassiat

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/823807 ,  H01L21/823835 ,  H01L29/7847

Abstract: One method herein includes forming a gate structure above an active area of a semiconductor substrate, forming sidewall spacer structures adjacent the gate structure, forming a masking layer that allows implantation of ions into the gate electrode but not into areas of the active region where source/drain regions for the transistor will be formed, performing a gate ion implantation process to form a gate ion implant region in the gate electrode and performing an anneal process. An N-type transistor including sidewall spacer structures positioned adjacent a gate structure, a plurality of source/drain regions for the transistor and a gate implant region positioned in a gate electrode, wherein the gate implant region is comprised of ions of phosphorous, arsenic or an implant material with an atomic size that is equal to or greater than the atomic size of phosphorous at a concentration level that falls within the range of 5e18-5e21 ions/cm3.

Abstract translation: 这里的一种方法包括在半导体衬底的有源区上方形成栅极结构，形成与栅极结构相邻的侧壁间隔结构，形成允许将离子注入栅电极但不进入有源区的源的/ 将形成用于晶体管的漏极区域，执行栅极离子注入工艺以在栅极电极中形成栅极离子注入区域并执行退火工艺。 一种N型晶体管，其包括邻近栅极结构定位的侧壁间隔结构，用于晶体管的多个源极/漏极区域和位于栅极电极中的栅极注入区域，其中栅极注入区域由磷，砷或 原子尺寸等于或大于磷离子浓度在5e18-5e21离子/ cm3范围内的原子尺寸的植入材料。

公开(公告)号：US20140319620A1

公开(公告)日：2014-10-30

申请号：US13874200

申请日：2013-04-30

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Nicolas Sassiat ,  Ralf Richter

IPC: H01L49/02 ,  H01L21/8234 ,  H01L27/06

CPC classification number: H01L28/20 ,  H01L27/0629 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66606 ,  H01L29/78

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes a first transistor structure that includes an etch-stop material layer, a first workfunction material layer disposed over the etch-stop material layer, a second workfunction material layer disposed over the first workfunction material layer, and a metal fill material disposed over the second workfunction material layer. The integrated circuit further includes a second transistor structure that includes a layer of the etch-stop material, a layer of the second workfunction material disposed over the etch-stop material layer, and a layer of the metal fill material disposed over the second workfunction material layer. Still further, the integrated circuit includes a resistor structure that includes a layer of the etch-stop material, a layer of the metal fill material disposed over the etch-stop material layer, and a silicon material layer disposed over the metal fill material layer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，集成电路包括第一晶体管结构，其包括蚀刻停止材料层，设置在蚀刻停止材料层上的第一功函数材料层，设置在第一功函数材料层上的第二功函数材料层，以及 设置在第二功函数材料层上的金属填充材料。 集成电路还包括第二晶体管结构，其包括蚀刻停止材料层，设置在蚀刻停止材料层上的第二功函件层，以及设置在第二功函数材料上的金属填充材料层 层。 此外，集成电路包括电阻器结构，其包括蚀刻停止材料层，设置在蚀刻停止材料层上的金属填充材料层以及设置在金属填充材料层上的硅材料层。