公开(公告)号：US20180323269A1

公开(公告)日：2018-11-08

申请号：US15585865

申请日：2017-05-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Jianwei Peng ,  Hsien-Ching Lo ,  Kwan-Yong Lim ,  Hui Zhan

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative method disclosed includes, among other things, forming a gate around an initial fin structure and above a layer of insulating material, and performing a fin trimming process on an exposed portion of the initial fin structure in the source/drain region so as to produce a reduced-size fin portion positioned above a surface of a layer of insulating material in the source/drain region of the device, wherein the the reduced-size fin portion has a second size that is less than the first size. In this example, the method also includes forming a conformal epi semiconductor material on the reduced-size fin portion and forming a conductive source/drain contact structure that is conductively coupled to and wrapped around the conformal epi semiconductor material

公开(公告)号：US20160126353A1

公开(公告)日：2016-05-05

申请号：US14526617

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Jody A. Fronheiser ,  Yi Qi ,  Sylvie Mignot

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/225 ,  H01L21/02 ,  H01L21/324 ,  H01L29/165 ,  H01L29/06

CPC classification number: H01L29/7851 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/18 ,  H01L21/324 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7842

Abstract: A method includes forming a fin on a semiconductor substrate and forming recesses on sidewalls of the fin. A silicon alloy material is formed in the recesses. A thermal process is performed to define a silicon alloy fin portion from the silicon alloy material and the fin. A semiconductor device includes a substrate, a fin defined on the substrate and an isolation structure disposed adjacent the fin. A first portion of the fin extending above the isolation structure has a substantially vertical sidewall and a different material composition than a second portion of the fin not extending above the isolation structure.

Abstract translation: 一种方法包括在半导体衬底上形成翅片并在翅片的侧壁上形成凹槽。 凹槽中形成硅合金材料。 进行热处理以从硅合金材料和翅片限定硅合金翅片部分。 半导体器件包括衬底，限定在衬底上的翅片和邻近翅片设置的隔离结构。 在隔离结构上方延伸的翅片的第一部分具有基本上垂直的侧壁和不同于在隔离结构上方延伸的翅片的第二部分的不同材料组成。

公开(公告)号：US20160118472A1

公开(公告)日：2016-04-28

申请号：US14867800

申请日：2015-09-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi

IPC: H01L29/66 ,  H01L29/06

CPC classification number: H01L29/66553 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/78696

Abstract: One illustrative method involves forming a FinFET device or a nanowire device by forming a sacrificial gate structure above a substantially vertically oriented structure comprised of first and second semiconductor materials, forming epi semiconductor material in the source/drain regions, removing the sacrificial gate structure so as to define a replacement gate cavity and to expose the first and second semiconductor materials within the gate cavity, performing an etching process through the replacement gate cavity to selectively remove the exposed first sacrificial semiconductor material relative to the exposed second semiconductor material so as to define a gap under the second semiconductor material within the gate cavity, filling the gap with an insulating material, and forming a replacement gate structure in the gate cavity.

Abstract translation: 一种说明性方法包括通过在由第一和第二半导体材料构成的基本垂直取向的结构上方形成牺牲栅极结构，形成FinFET器件或纳米线器件，在源极/漏极区域形成外延半导体材料，去除牺牲栅极结构，以便 以限定替换栅极腔并且暴露栅极腔内的第一和第二半导体材料，通过替代栅极腔执行蚀刻工艺，以相对于暴露的第二半导体材料选择性地去除暴露的第一牺牲半导体材料，以便限定 在栅腔内的第二半导体材料下面的间隙，用绝缘材料填充间隙，并在栅腔中形成替换栅极结构。

公开(公告)号：US20160035630A1

公开(公告)日：2016-02-04

申请号：US14882640

申请日：2015-10-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vara G. Reddy Vakada ,  Laegu Kang ,  Michael Ganz ,  Yi Qi ,  Puneet Khanna ,  Srikanth Balaji Samavedam ,  Sri Charan Vemula ,  Manfred Eller

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823892 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/0928

Abstract: One illustrative method disclosed herein includes performing a first plurality of epitaxial deposition processes to form a first plurality of semiconductor materials selectively above the N-active region while masking the P-active region, performing a second plurality of epitaxial deposition processes to form a second plurality of semiconductor materials selectively above the P-active region while masking the N-active region, forming an N-type transistor in and above the N-active region and forming a P-type transistor in and above the P-active region.

Abstract translation: 本文公开的一种说明性方法包括执行第一多个外延沉积工艺，以在掩蔽P活性区域的同时，选择性地在N活性区域上方形成第一多个半导体材料，进行第二多个外延沉积工艺以形成第二多个 半导体材料选择性地在P有源区上方，同时掩蔽N有源区，在N-有源区中和上方形成N型晶体管，并在P-活性区中和上方形成P型晶体管。

公开(公告)号：US20150318176A1

公开(公告)日：2015-11-05

申请号：US14267154

申请日：2014-05-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Ajey Poovannummoottil Jacob ,  Shurong Liang

IPC: H01L21/265 ,  H01L29/165 ,  H01L29/78 ,  H01L21/306 ,  H01L21/02 ,  H01L21/324 ,  H01L29/66 ,  H01L29/167

CPC classification number: H01L21/26513 ,  H01L21/02636 ,  H01L21/26506 ,  H01L21/30608 ,  H01L21/324 ,  H01L29/165 ,  H01L29/167 ,  H01L29/6681 ,  H01L29/7849

Abstract: One method disclosed includes removing at least a portion of a fin to thereby define a fin trench in a layer of insulating material, forming a substantially defect-free first layer of semiconductor material in the fin trench, forming a second layer of semiconductor material on an as-formed upper surface of the first layer of semiconductor material, forming an implant region at the interface between the first layer of semiconductor material and the substrate, performing an anneal process to induce defect formation in at least the first layer of semiconductor material, forming a third layer of semiconductor material on the second layer of semiconductor material, forming a layer of channel semiconductor material on the third layer of semiconductor material, and forming a gate structure around at least a portion of the channel semiconductor material.

Abstract translation: 公开的一种方法包括去除鳍片的至少一部分，从而在绝缘材料层中限定翅片沟槽，在翅片沟槽中形成基本上无缺陷的半导体材料层，在第二层半导体材料上形成第二层半导体材料 形成第一半导体材料层的上表面，在第一半导体材料层和衬底之间的界面处形成注入区域，执行退火工艺以在至少第一半导体材料层中形成缺陷，形成 在所述第二半导体材料层上的第三层半导体材料，在所述第三半导体材料层上形成沟道半导体材料层，以及围绕所述沟道半导体材料的至少一部分形成栅极结构。

公开(公告)号：US20150279959A1

公开(公告)日：2015-10-01

申请号：US14242529

申请日：2014-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Ajey Poovannummoottil Jacob

IPC: H01L29/66

CPC classification number: H01L21/823431

Abstract: One illustrative method disclosed herein includes, among other things, forming a region of a sacrificial material in a semiconductor substrate at a location where the portion of the fin to be removed will be located, after forming the region of sacrificial material, performing at least one first etching process to form a plurality of fin-formation trenches that define the fin, wherein at least a portion of the fin is comprised of the sacrificial material, and performing at least one second etching process to selectively remove substantially all of the sacrificial material portion of the fin relative to the substrate.

Abstract translation: 本文中公开的一种说明性方法包括在形成牺牲材料区域之后，在要被去除的翅片的部分将被定位的位置处在半导体衬底中形成牺牲材料的区域，执行至少一个 第一蚀刻工艺以形成限定翅片的多个翅片形成沟槽，其中鳍片的至少一部分由牺牲材料构成，并且执行至少一个第二蚀刻工艺以选择性地移除基本上所有的牺牲材料部分 的翅片相对于基底。