公开(公告)号：US07318993B2

公开(公告)日：2008-01-15

申请号：US10499417

申请日：2002-12-10

申请人： Rodger Fehlhaber ,  Helmut Tews

发明人： Rodger Fehlhaber ,  Helmut Tews

IPC分类号： G03C5/00

CPC分类号： B81C1/00396 ,  G03F1/50 ,  G03F7/2045 ,  G03F7/2065 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/2652 ,  H01L21/3086 ,  H01L21/32139

摘要： A resistless lithography method for fabricating fine stiuctures is disclosed. IN an embodiment, a semiconductor mask layer (HM) may be formed on a carrier material (TM, HM′) and a selective ion implantation (I) being effected in order to dope selected regions (1) of the semiconductor mask layer (HM). Wet chemical removal of the non doped regions of the semiconductor mask layer (HM) yields a semiconductor mask which can be used for further patterning. A simple and high precision resistless lithography method for structures smaller than 100 nm is obtained in this way.

摘要翻译： 公开了一种用于制造精细结构的抗蚀刻光刻方法。 在一个实施例中，可以在载体材料（TM，HM'）和选择性离子注入（I）上形成半导体掩模层（HM），以便掺杂半导体掩模层（HM）的选定区域（1） ）。 半导体掩模层（HM）的非掺杂区域的湿化学除去产生可用于进一步图案化的半导体掩模。 以这种方式获得用于小于100nm的结构的简单且高精度的无电阻光刻方法。

公开(公告)号：US20070155090A1

公开(公告)日：2007-07-05

申请号：US11652157

申请日：2007-01-11

申请人： Hans-Joachim Barth ,  Helmut Tews

发明人： Hans-Joachim Barth ,  Helmut Tews

IPC分类号： H01L21/8242 ,  H01L21/20

CPC分类号： H01L23/5223 ,  H01L27/0805 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention relates to a method for producing a capacitor arrangement, and to a corresponding capacitor arrangement, wherein the first insulating layer is formed at the surface of a carrier substrate and a first capacitor electrode with a multiplicity of interspaced first interconnects is produced in said insulating layer. Using a mask layer, partial regions of the first insulating layer are removed for the purpose of uncovering the multiplicity of first interconnects, and after the formation of a capacitor dielectric at the surface of the uncovered first interconnects, a second capacitor electrode is formed with a multiplicity of interspaced second interconnects lying between the first interconnects coated with capacitor dielectric. This additionally simplified production method enables self-aligning and cost-effective production of capacitors having a high capacitance per unit area and mechanical stability.

摘要翻译： 本发明涉及一种用于制造电容器装置的方法和相应的电容器装置，其中第一绝缘层形成在载体衬底的表面，并且在所述绝缘体中产生具有多个间隔第一互连的第一电容器电极 层。 使用掩模层，为了揭露多个第一互连的目的，除去第一绝缘层的部分区域，并且在未覆盖的第一互连件的表面上形成电容器电介质之后，形成第二电容器电极 位于涂覆有电容器电介质的第一互连之间的间隔第二互连的多重性。 这种另外简化的制造方法能够实现具有每单位面积的高电容和机械稳定性的电容器的自对准和成本有效的生产。

公开(公告)号：US07169677B2

公开(公告)日：2007-01-30

申请号：US10519201

申请日：2003-05-14

申请人： Helmut Tews

发明人： Helmut Tews

IPC分类号： H01L21/336 ,  H01L21/425 ,  H01L21/338

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/518

摘要： A method for fabricating a spacer structure includes: forming a gate insulation layer having a gate deposition-inhibiting layer, a gate layer and a covering deposition-inhibiting layer on a semiconductor substrate, and patterning the gate layer and the covering deposition-inhibiting layer in order to form gate stacks. An insulation layer is deposited selectively using the deposition-inhibiting layers, thereby permitting highly accurate formation of the spacer structure.

摘要翻译： 一种用于制造间隔结构的方法包括：在半导体衬底上形成具有栅极沉积抑制层，栅极层和覆盖沉积抑制层的栅极绝缘层，并将栅极层和覆盖物沉积抑制层图案化 命令形成门堆栈。 使用沉积抑制层选择性地沉积绝缘层，从而允许高度精确地形成间隔物结构。

公开(公告)号：US07129152B2

公开(公告)日：2006-10-31

申请号：US10520743

申请日：2003-06-21

申请人： Rodger Fehlhaber ,  Helmut Tews

发明人： Rodger Fehlhaber ,  Helmut Tews

IPC分类号： H01L21/338

CPC分类号： H01L29/66545 ,  H01L21/28141 ,  H01L29/6656 ,  H01L29/6659

摘要： A method for fabricating a short channel field-effect transistor is presented. A sublithographic gate sacrificial layer is formed, as are spacers at the side walls of the gate sacrificial layer. The gate sacrificial layer is removed to form a gate recess and a gate dielectric and a control layer are formed in the gate recess. The result is a short channel field-effect transistor with minimal fluctuations in the critical dimensions in a range below 100 nanometers.

摘要翻译： 提出了一种用于制造短沟道场效应晶体管的方法。 在栅极牺牲层的侧壁处形成间隔物，形成亚光刻栅牺牲层。 去除栅极牺牲层以形成栅极凹部，并且在栅极凹部中形成栅极电介质和控制层。 结果是短通道场效应晶体管，其临界尺寸的波动在100纳米以下的范围内。

公开(公告)号：US20060211264A1

公开(公告)日：2006-09-21

申请号：US10521528

申请日：2003-06-12

申请人： Ronald Kakoschke ,  Helmut Tews

发明人： Ronald Kakoschke ,  Helmut Tews

IPC分类号： H01L21/31

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L29/66666 ,  H01L29/7827

摘要： A vertical field-effect transistor having a semiconductor layer, in which a doped channel region is arranged along a depression. A “buried” terminal region leads as far as a surface of the semiconductor layer. The field-effect transistor also has a doped terminal region near an opening of the depression as well as the doped terminal region remote from the opening, a control region arranged in the depression, and an electrical insulating region between the control region and the channel region. The terminal region remote from the opening leads as far as a surface containing the opening or is electrically conductively connected to an electrically conductive connection leading to the surface. The control region is arranged in only one depression. The field-effect transistor is a drive transistor at a word line or at a bit line of a memory cell array.

摘要翻译： 具有半导体层的垂直场效应晶体管，其中掺杂沟道区沿着凹陷布置。 “埋入”端子区域导通至半导体层的表面。 场效应晶体管还具有靠近凹陷的开口的掺杂端子区域以及远离开口的掺杂端子区域，布置在凹陷中的控制区域以及控制区域和沟道区域之间的电绝缘区域 。 远离开口的端子区域引出至包含开口的表面，或者导电地连接到通向该表面的导电连接。 控制区域仅布置在一个凹部中。 场效应晶体管是位于存储单元阵列的字线或位线处的驱动晶体管。

公开(公告)号：US20060094176A1

公开(公告)日：2006-05-04

申请号：US10520743

申请日：2003-06-21

申请人： Rodger Fehlhaber ,  Helmut Tews

发明人： Rodger Fehlhaber ,  Helmut Tews

IPC分类号： H01L21/338 ,  H01L21/8234

CPC分类号： H01L29/66545 ,  H01L21/28141 ,  H01L29/6656 ,  H01L29/6659

摘要： The invention relates to a method for fabricating a short channel field-effect transistor, comprising the steps of: forming a sublithographic gate sacrificial layer (3M), forming spacers (7S) at the side walls of the gate sacrificial layer (3M), removing the gate sacrificial layer (3M) to form a gate recess and forming a gate dielectric (10) and a control layer (11) in the gate recess. The result is a short channel FET with minimal fluctuations in the critical dimensions in a range below 100 nanometers.

摘要翻译： 本发明涉及一种用于制造短沟道场效应晶体管的方法，包括以下步骤：形成亚光栅牺牲层（3M），在栅极牺牲层（3M）的侧壁处形成间隔物（7S） ），去除栅极牺牲层（3M）以形成栅极凹槽，并在栅极凹部中形成栅极电介质（10）和控制层（11）。 结果是在100纳米以下的临界尺寸波动较小的短通道FET。

公开(公告)号：US20060084234A1

公开(公告)日：2006-04-20

申请号：US10519201

申请日：2003-05-14

申请人： Helmut Tews

发明人： Helmut Tews

IPC分类号： H01L21/336

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/518

摘要： A method for fabricating a spacer structure includes: forming a gate insulation layer having a gate deposition-inhibiting layer, a gate layer and a covering deposition-inhibiting layer on a semiconductor substrate, and patterning the gate layer and the covering deposition-inhibiting layer in order to form gate stacks. An insulation layer is deposited selectively using the deposition-inhibiting layers, thereby permitting highly accurate formation of the spacer structure.

摘要翻译： 一种用于制造间隔结构的方法包括：在半导体衬底上形成具有栅极沉积抑制层，栅极层和覆盖沉积抑制层的栅极绝缘层，并且将栅极层和覆盖物沉积抑制层图案化 命令形成门堆栈。 使用沉积抑制层选择性地沉积绝缘层，从而允许高度精确地形成间隔物结构。

公开(公告)号：US5436475A

公开(公告)日：1995-07-25

申请号：US246481

申请日：1994-05-19

申请人： Helmut Tews ,  Hans-Peter Zwicknagl

发明人： Helmut Tews ,  Hans-Peter Zwicknagl

IPC分类号： H01L21/331 ,  H01L29/417 ,  H01L29/73 ,  H01L29/737 ,  H01L29/161 ,  H01L29/205 ,  H01L29/225

CPC分类号： H01L29/7371 ,  H01L29/41708 ,  H01L29/73

摘要： A power transistor has a plurality of small emitter-base complexes arranged in an array. These complexes are electrically insulated from the surrounding semiconductor material by separating regions such that for the current supply to the collectors, a joint subcollector layer and thereupon a collector metallization exist outside of the emitter-base complexes and reaching up to the separating regions. The individual emitter-base complexes are electrically connected with each other via strip-shaped base supply lines and strip-shaped emitter supply lines, and also with a base contact surface and an emitter contact surface.

摘要翻译： 功率晶体管具有排列成阵列的多个小的发射极 - 基极复合体。 这些络合物通过分离区域与周围半导体材料电绝缘，使得对于集电体的电流供应，接合子集电极层和集电极金属化存在于发射极 - 基极复合体之外并且达到分离区域。 单独的发射极 - 基极复合体通过条形基极电源线和条形发射器电源线以及基极接触表面和发射极接触表面彼此电连接。

公开(公告)号：US5274266A

公开(公告)日：1993-12-28

申请号：US15040

申请日：1993-02-08

申请人： Helmut Tews ,  Hans-Peter Zwicknagl

发明人： Helmut Tews ,  Hans-Peter Zwicknagl

IPC分类号： H01L21/335 ,  H01L29/772 ,  H01L29/72

CPC分类号： H01L29/66424 ,  H01L29/66454 ,  H01L29/7722

摘要： A permeable base transistor has an emitter layer or emitter layer sequence composed of a semiconductor material which has a greater energy band gap than a semiconductor material of a base layer. This emitter layer or emitter layer sequence is selectively grown into an opening of the base layer and onto a collector layer situated therebelow.

摘要翻译： 可渗透的基极晶体管具有由半导体材料构成的发射极层或发射极层序列，该半导体材料具有比基底层的半导体材料更大的能带隙。 该发射极层或发射极层序列被选择性地生长到基底层的开口中并位于其下方的集电极层上。

公开(公告)号：US5093272A

公开(公告)日：1992-03-03

申请号：US620625

申请日：1990-12-03

申请人： Joachim Hoepfner ,  Helmut Tews ,  Hans-Peter Zwicknagl

发明人： Joachim Hoepfner ,  Helmut Tews ,  Hans-Peter Zwicknagl

IPC分类号： H01L29/73 ,  H01L21/28 ,  H01L21/331 ,  H01L29/205 ,  H01L29/737

CPC分类号： H01L29/66318 ,  H01L21/28 ,  Y10S148/01 ,  Y10S438/951

摘要： Method for manufacturing a self-aligned emitter-base complex whereby a sequence of epitaxial layers, which corresponds to the optimal base-emitter layer sequence in the re-etched part of the heterobipolar transistor is grown. Subsequently, the base implantation is introduced using a dummy-emitter as a mask. Using a dielectric mask covering the region not covered by the dummy-emitter, after the removal of the dummy-emitter the emitter contact layers are selectively grown in its region. The contacting is then provided.

摘要翻译： 用于制造自对准发射极 - 基极复合体的方法，由此生长对应于异质双极晶体管的再蚀刻部分中的最佳基极 - 发射极层序列的外延层序列。 随后，使用伪发射极作为掩模引入基极注入。 使用覆盖未被虚拟 - 发射极覆盖的区域的介电掩模，在去除虚拟 - 发射极之后，在其区域中选择性地生长发射极接触层。 然后提供接触。