公开(公告)号：US08743610B2

公开(公告)日：2014-06-03

申请号：US13171667

申请日：2011-06-29

申请人： Jin-Ki Kim ,  Hong Beom Pyeon

发明人： Jin-Ki Kim ,  Hong Beom Pyeon

IPC分类号： G11C16/00

CPC分类号： G06F3/0611 ,  G06F3/0655 ,  G06F3/0688 ,  G06F13/4243 ,  G11C5/066 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/10 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459 ,  G11C2207/107 ,  G11C2216/30

摘要： An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

摘要翻译： 公开了一种用于控制半导体存储器中的多个串行数据链路接口和多个存储体之间的数据传输的装置，系统和计算机实现的方法。 在一个示例中，公开了具有多个链路和存储体的闪存器件，其中链路独立于存储体。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。 此外，描述了虚拟多链路配置，其中使用单个链路来模拟多个链路。

公开(公告)号：US07978518B2

公开(公告)日：2011-07-12

申请号：US12337038

申请日：2008-12-17

申请人： Hong-Beom Pyeon ,  Jin-Ki Kim

发明人： Hong-Beom Pyeon ,  Jin-Ki Kim

IPC分类号： G11C16/04

CPC分类号： G11C16/3427 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/30

摘要： Each memory cell string in a generic NAND flash cell block connects to a Common Source Line (CLS). A value for applying to the CSL is centrally generated and distributed to a local switch logic unit corresponding to each NAND flash cell block. For source-line page programming, the distribution line may be called a Global Common Source Line (GCSL). In an array of NAND flash cell blocks, only one NAND flash cell block is selected at a time for programming. To reduce power consumption, only the selected NAND flash cell block receives a value on the CSL that is indicative of the value on the GCSL. Additionally, the CSLs of non-selected NAND flash cell blocks may be disabled through an active connection to ground.

摘要翻译： 通用NAND闪存单元块中的每个存储单元串连接到公共源线（CLS）。 集中生成用于应用于CSL的值并将其分配给对应于每个NAND闪存单元块的本地开关逻辑单元。 对于源行页面编程，分发线可以称为全局公用源线（GCSL）。 在NAND闪存单元块的阵列中，一次仅选择一个NAND闪存单元块进行编程。 为了降低功耗，只有选定的NAND闪存单元块才接收到指示GCSL上的值的CSL上的值。 此外，未选择的NAND闪存单元块的CSL可以通过主动连接到地来禁用。

公开(公告)号：US08549209B2

公开(公告)日：2013-10-01

申请号：US12508926

申请日：2009-07-24

申请人： Hong Beom Pyeon ,  Jin-Ki Kim ,  Peter B. Gillingham

发明人： Hong Beom Pyeon ,  Jin-Ki Kim ,  Peter B. Gillingham

IPC分类号： G06F13/00

CPC分类号： G06F12/0238 ,  G06F3/0634 ,  G06F12/04 ,  G06F12/0646 ,  G06F13/36 ,  G06F13/4234 ,  G06F13/4291 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/1087

摘要： A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. The bridge device has memory organized as banks, where each bank is configured to have a virtual page size that is less than the maximum physical size of the page buffer. Therefore only a segment of data corresponding to the virtual page size stored in the page buffer is transferred to the bank. The virtual page size of the banks is provided in a virtual page size (VPS) configuration command having an ordered structure where the position of VPS data fields containing VPS configuration codes in the command correspond to different banks which are ordered from a least significant bank to a most significant bank. The VPS configuration command is variable in size, and includes only the VPS configuration codes for the highest significant bank being configured and the lower significant banks.

摘要翻译： 一种复合存储器件，包括分立存储器件和用于控制分立存储器件的桥接器件。 桥接器件具有组织为存储体的存储器，其中每个存储体被配置为具有小于页面缓冲器的最大物理大小的虚拟页面大小。 因此，只有与存储在页面缓冲器中的虚拟页大小相对应的数据段被传送到存储体。 以具有有序结构的虚拟页面大小（VPS）配置命令提供虚拟页面大小，其中在命令中包含VPS配置代码的VPS数据字段的位置对应于从最不重要的银行排序到不同的银行， 最重要的银行。 VPS配置命令的大小是可变的，并且只包括配置的最高有效存储库的VPS配置代码和较低的重要库。

公开(公告)号：US08537617B2

公开(公告)日：2013-09-17

申请号：US13365913

申请日：2012-02-03

申请人： Jin-Ki Kim ,  Hong Beom Pyeon

发明人： Jin-Ki Kim ,  Hong Beom Pyeon

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/10

摘要： A method for programming a NAND flash string. In the present method, wordlines are driven to a first pass voltage for coupling a string precharge voltage provided by a source line to the memory cells, where the string precharge voltage is greater than the first pass voltage. With the exception a first wordline corresponding to a first memory cell adjacent to a selected memory cell, all the other wordlines are driven to a second pass voltage greater than the first pass voltage. The first memory cell is positioned between the selected memory cell and a string select device. A second wordline corresponding to a second memory cell adjacent to the selected memory cell is driven to a first supply voltage for turning off the second memory cell. A third wordline corresponding to the selected memory cell is driven to a programming voltage greater than the second pass voltage. A bitline is then coupled to the selected memory cell.

摘要翻译： 一种用于编程NAND闪存串的方法。 在本方法中，字线被驱动到第一通过电压，用于将由源极线提供的串预充电电压耦合到存储器单元，其中串预充电电压大于第一通过电压。 除了对应于与所选择的存储器单元相邻的第一存储单元的第一字线外，所有其它字线被驱动到大于第一通过电压的第二通过电压。 第一存储器单元位于所选存储单元和字符串选择器件之间。 对应于与所选存储单元相邻的第二存储单元的第二字线被驱动到用于关闭第二存储单元的第一电源电压。 对应于所选存储单元的第三字线被驱动到大于第二通过电压的编程电压。 然后将位线耦合到所选择的存储器单元。

公开(公告)号：US08351265B2

公开(公告)日：2013-01-08

申请号：US13249744

申请日：2011-09-30

申请人： Hong Beom Pyeon ,  Jin-Ki Kim

发明人： Hong Beom Pyeon ,  Jin-Ki Kim

IPC分类号： G11C16/04

CPC分类号： G11C16/30 ,  G11C5/145 ,  G11C5/147 ,  H02M3/073

摘要： Power supplies in flash memory devices are disclosed. A first section of a flash memory device includes non-volatile memory for storing data. A second section of the flash memory device includes at least first and second pumping circuits. The first pumping circuit receives a first voltage and produces, at an output of the first pumping circuit, a second voltage at a second voltage level that is higher than the first voltage level. The second pumping circuit has an input coupled to the first pumping circuit output for cooperatively employing the first pumping circuit to pump up from a voltage greater than the first voltage to produce a third voltage at a third voltage level that is higher than the second voltage level.

摘要翻译： 公开了闪存设备中的电源。 闪存器件的第一部分包括用于存储数据的非易失性存储器。 闪存器件的第二部分至少包括第一和第二泵浦电路。 第一泵送电路接收第一电压，并且在第一泵送电路的输出处产生高于第一电压电平的第二电压电平的第二电压。 第二泵浦电路具有耦合到第一泵浦电路输出的输入端，用于协同地采用第一泵浦电路从大于第一电压的电压泵浦，以产生高于第二电压电平的第三电压电平的第三电压 。

公开(公告)号：US20110032773A1

公开(公告)日：2011-02-10

申请号：US12903271

申请日：2010-10-13

申请人： Hong Beom Pyeon ,  Jin-Ki Kim

发明人： Hong Beom Pyeon ,  Jin-Ki Kim

IPC分类号： G11C16/30 ,  G11C16/04

CPC分类号： G11C16/30 ,  G11C5/145 ,  G11C5/147 ,  H02M3/073

摘要： Power supplies in flash memory devices are disclosed. A first section of a flash memory device includes non-volatile memory for storing data. A second section of the flash memory device includes at least first and second pumping circuits. The first pumping circuit receives a first voltage and produces, at an output of the first pumping circuit, a second voltage at a second voltage level that is higher than the first voltage level. The second pumping circuit has an input coupled to the first pumping circuit output for cooperatively employing the first pumping circuit to pump up from a voltage greater than the first voltage to produce a third voltage at a third voltage level that is higher than the second voltage level.

摘要翻译： 公开了闪存设备中的电源。 闪存器件的第一部分包括用于存储数据的非易失性存储器。 闪存器件的第二部分至少包括第一和第二泵浦电路。 第一泵送电路接收第一电压，并且在第一泵送电路的输出处产生高于第一电压电平的第二电压电平的第二电压。 第二泵浦电路具有耦合到第一泵浦电路输出的输入端，用于协同地采用第一泵浦电路从大于第一电压的电压泵浦，以产生高于第二电压电平的第三电压电平的第三电压 。

公开(公告)号：US07652922B2

公开(公告)日：2010-01-26

申请号：US11324023

申请日：2005-12-30

申请人： Jin-Ki Kim ,  Hong Beom Pyeon

发明人： Jin-Ki Kim ,  Hong Beom Pyeon

IPC分类号： G11C16/00

CPC分类号： G06F3/0611 ,  G06F3/0655 ,  G06F3/0688 ,  G06F13/4243 ,  G11C5/066 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/10 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459 ,  G11C2207/107 ,  G11C2216/30

摘要： An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

摘要翻译： 公开了一种用于控制半导体存储器中的多个串行数据链路接口和多个存储体之间的数据传输的装置，系统和计算机实现的方法。 在一个示例中，公开了具有多个链路和存储体的闪存器件，其中链路独立于存储体。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。 此外，描述了虚拟多链路配置，其中使用单个链路来模拟多个链路。

公开(公告)号：US07916569B2

公开(公告)日：2011-03-29

申请号：US12339946

申请日：2008-12-19

申请人： Jin-Ki Kim ,  HakJune Oh

发明人： Jin-Ki Kim ,  HakJune Oh

IPC分类号： G11C7/00

CPC分类号： G11C11/40615 ,  G11C11/406 ,  G11C11/40607 ,  G11C11/40618 ,  G11C11/40622

摘要： A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application.

摘要翻译： 动态随机存取存储器件包括多个存储器子块。 每个子块具有连接多个数据存储单元的多个字线。 部分阵列自刷新（PASR）配置设置是独立制作的。 根据PASR设置，内存子块被寻址以进行刷新。 PASR设置由内存控制器进行。 可以选择子块地址的任何种类的组合。 因此，存储器子块被完全独立地刷新。 用于数据保留的用户可选择的存储器阵列特别为低功耗移动应用提供有效的存储器控​​制编程

公开(公告)号：US10236032B2

公开(公告)日：2019-03-19

申请号：US12212902

申请日：2008-09-18

申请人： HakJune Oh ,  Jin-Ki Kim

发明人： HakJune Oh ,  Jin-Ki Kim

IPC分类号： G11C5/04 ,  G11C5/02 ,  G11C7/10

摘要： A mass data storage system, which comprises: a controller for issuing and receiving signals to carry out memory operations; a motherboard comprising at least one first connector and providing signal pathways for establish a ring from the controller via each of the at least one first connector and back to the controller; and at least one non-volatile memory module comprising a second connector electrically connected to a chain of non-volatile memory devices, wherein mating of the second connector with a given one of the at least one first connector causes the chain of non-volatile memory devices to be inserted into the ring, thereby to allow the controller to carry out the memory operations on the non-volatile memory devices in the chain.

公开(公告)号：US20100067278A1

公开(公告)日：2010-03-18

申请号：US12212902

申请日：2008-09-18

申请人： HakJune Oh ,  Jin-Ki Kim

发明人： HakJune Oh ,  Jin-Ki Kim

IPC分类号： G11C5/02 ,  G06F13/00

CPC分类号： G11C5/04 ,  G06F2212/205 ,  G11C5/02 ,  G11C7/1003

摘要： A mass data storage system, which comprises: a controller for issuing and receiving signals to carry out memory operations; a motherboard comprising at least one first connector and providing signal pathways for establish a ring from the controller via each of the at least one first connector and back to the controller; and at least one non-volatile memory module comprising a second connector electrically connected to a chain of non-volatile memory devices, wherein mating of the second connector with a given one of the at least one first connector causes the chain of non-volatile memory devices to be inserted into the ring, thereby to allow the controller to carry out the memory operations on the non-volatile memory devices in the chain.

摘要翻译： 一种大容量数据存储系统，包括：用于发出和接收信号以执行存储器操作的控制器; 主板，包括至少一个第一连接器，并提供信号路径，用于通过所述至少一个第一连接器中的每一个从所述控制器建立环并返回到所述控制器; 以及至少一个非易失性存储器模块，其包括电连接到一系列非易失性存储器件的第二连接器，其中所述第二连接器与所述至少一个第一连接器中的给定的一个配合使得所述非易失性存储器链 设备插入到环中，从而允许控制器对链中的非易失性存储设备执行存储器操作。