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    Bridge device architecture for connecting discrete memory devices to a system
    1.
    发明授权
    Bridge device architecture for connecting discrete memory devices to a system 有权
    用于将分立存储器件连接到系统的桥接器件架构

    公开(公告)号：US08363444B2

    公开(公告)日：2013-01-29

    申请号：US13365895

    申请日：2012-02-03

    申请人： Jin-Ki Kim ,  HakJune Oh ,  Hong Beom Pyeon

    发明人： Jin-Ki Kim ,  HakJune Oh ,  Hong Beom Pyeon

    IPC分类号： G11C7/02

    CPC分类号： G11C5/02 ,  G06F13/4234 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1003 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2924/15311

    摘要： A bridge device architecture for connecting discrete memory devices. The bridge device is used in conjunction with a composite memory device including at least one discrete memory device. The bridge device includes a local control interface for connecting to the at least one discrete memory device, a local input/output interface for connecting to the at least one discrete memory device, and a global input/output interface. The global input/output interface receives and provides global memory control signals and also receives and provides write data to and read data from the at least one discrete memory device.

    摘要翻译： 用于连接分立存储器件的桥接器件架构。 桥接器件与包括至少一个分立存储器件的复合存储器件结合使用。 桥接器件包括用于连接至少一个分立存储器件的本地控制接口，用于连接至少一个分立存储器件的本地输入/输出接口以及全局输入/输出接口。 全局输入/输出接口接收并提供全局存储器控制信号，并且还接收并向至少一个离散存储器件提供写入数据和从其读取数据。

    Apparatus and method of page program operation for memory devices with mirror back-up of data
    2.
    发明授权
    Apparatus and method of page program operation for memory devices with mirror back-up of data 失效
    具有镜像备份数据的存储器件的页面编程操作的装置和方法

    公开(公告)号：US08060691B2

    公开(公告)日：2011-11-15

    申请号：US13022166

    申请日：2011-02-07

    申请人： Hong Beom Pyeon ,  Jin-Ki Kim ,  HakJune Oh

    发明人： Hong Beom Pyeon ,  Jin-Ki Kim ,  HakJune Oh

    IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F3/00 ,  G06F5/00

    CPC分类号： G06F13/4243 ,  G06F13/4247

    摘要： An apparatus and method of page program operation is provided. When performing a page program operation with a selected memory device, a memory controller loads the data into the page buffer of one selected memory device and also into the page buffer of another selected memory device in order to store a back-up copy of the data. In the event that the data is not successfully programmed into the memory cells of the one selected memory device, then the memory controller recovers the data from the page buffer of the other memory device. Since a copy of the data is stored in the page buffer of the other memory device, the memory controller does not need to locally store the data in its data storage elements.

    摘要翻译： 提供了一种页面编程操作的装置和方法。 当使用所选择的存储器件执行页面编程操作时，存储器控制器将数据加载到一个所选择的存储器件的页面缓冲器中，并将其加载到另一个选择的存储器件的页面缓冲器中，以便存储数据的备份副本 。 在数据未成功编程到所选存储器件的存储器单元中的情况下，存储器控制器从另一存储器件的页缓冲器中恢复数据。 由于数据的副本存储在另一存储器件的页缓冲器中，所以存储器控制器不需要将数据本地存储在其数据存储元件中。

    Dynamic random access memory with fully independent partial array refresh function
    3.
    发明授权
    Dynamic random access memory with fully independent partial array refresh function 有权
    具有完全独立的部分阵列刷新功能的动态随机存取存储器

    公开(公告)号：US07916569B2

    公开(公告)日：2011-03-29

    申请号：US12339946

    申请日：2008-12-19

    申请人： Jin-Ki Kim ,  HakJune Oh

    发明人： Jin-Ki Kim ,  HakJune Oh

    IPC分类号： G11C7/00

    CPC分类号： G11C11/40615 ,  G11C11/406 ,  G11C11/40607 ,  G11C11/40618 ,  G11C11/40622

    摘要： A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application.

    摘要翻译： 动态随机存取存储器件包括多个存储器子块。 每个子块具有连接多个数据存储单元的多个字线。 部分阵列自刷新（PASR）配置设置是独立制作的。 根据PASR设置，内存子块被寻址以进行刷新。 PASR设置由内存控制器进行。 可以选择子块地址的任何种类的组合。 因此，存储器子块被完全独立地刷新。 用于数据保留的用户可选择的存储器阵列特别为低功耗移动应用提供有效的存储器控​​制编程

    Memory with output control
    4.
    发明授权
    Memory with output control 有权
    内存带输出控制

    公开(公告)号：US07515471B2

    公开(公告)日：2009-04-07

    申请号：US11583354

    申请日：2006-10-19

    申请人： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

    发明人： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C2207/107

    摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

    摘要翻译： 公开了一种用于控制向半导体存储器中的串行数据链路接口的输出端口传送数据的装置，系统和方法。 在一个示例中，闪存设备可以具有多个串行数据链路，多个存储器组和控制输入端口，其使得存储器设备能够将串行数据传送到存储器件的串行数据输出端口。 在另一示例中，闪存器件可以具有单个串行数据链路，单个存储体，串行数据输入端口，用于接收输出使能信号的控制输入端口。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。

    APPARATUS AND METHOD FOR PRODUCING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES OF MIXED TYPE
    5.
    发明申请
    APPARATUS AND METHOD FOR PRODUCING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES OF MIXED TYPE 有权
    用于生产混合类型的串联互连设备的设备标识符的装置和方法

    公开(公告)号：US20080181214A1

    公开(公告)日：2008-07-31

    申请号：US11692452

    申请日：2007-03-28

    申请人： Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim ,  Shuji Sumi

    发明人： Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim ,  Shuji Sumi

    IPC分类号： H04L12/56

    CPC分类号： G06F13/4243

    摘要： A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR- and AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) as a packet are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. In a case of no-match, the ID generation is skipped and no ID is generated for another device. The DT is combined with the generated or the received ID depending on the device type match determination. The combined DT and ID is as a packet transferred to a next device. Such a device type match determination and ID generation or skip are performed in all devices of the several interconnection. With reference to device type provided to the interconnected devices, IDs are sequentially generated. The SI containing the DT, the ID and an ID generation command is transmitted in a packet basis to a next device.

    摘要翻译： 多个混合型存储器件（例如，DRAM，SRAM，MRAM以及NAND-，NOR-和AND-型闪存）被串联连接。 每个设备都有其设备类型的设备类型信息。 作为分组的串行输入（SI）中包含的特定设备类型（DT）和设备标识符（ID）被馈送到串行互连的一个设备。 设备确定馈送的DT是否匹配设备的DT。 在匹配的情况下，包含在该设备中的计算器执行计算以生成另一设备的ID，并且将馈送的ID锁存在设备的寄存器中。 在不匹配的情况下，跳过ID生成，并且不为另一设备生成ID。 根据设备类型匹配确定，DT与所生成或接收的ID组合。 组合的DT和ID作为传送到下一个设备的分组。 在多个互连的所有设备中执行这样的设备类型匹配确定和ID生成或跳过。 参考提供给互连设备的设备类型，依次生成ID。 将包含DT，ID和ID生成命令的SI以分组的形式发送到下一个设备。

    Mass data storage system with non-volatile memory modules
    6.
    发明授权
    Mass data storage system with non-volatile memory modules 有权

    公开(公告)号：US10236032B2

    公开(公告)日：2019-03-19

    申请号：US12212902

    申请日：2008-09-18

    申请人： HakJune Oh ,  Jin-Ki Kim

    发明人： HakJune Oh ,  Jin-Ki Kim

    IPC分类号： G11C5/04 ,  G11C5/02 ,  G11C7/10

    摘要： A mass data storage system, which comprises: a controller for issuing and receiving signals to carry out memory operations; a motherboard comprising at least one first connector and providing signal pathways for establish a ring from the controller via each of the at least one first connector and back to the controller; and at least one non-volatile memory module comprising a second connector electrically connected to a chain of non-volatile memory devices, wherein mating of the second connector with a given one of the at least one first connector causes the chain of non-volatile memory devices to be inserted into the ring, thereby to allow the controller to carry out the memory operations on the non-volatile memory devices in the chain.

    System and method of operating memory devices of mixed type
    9.
    发明授权
    System and method of operating memory devices of mixed type 有权
    操作混合型存储器件的系统和方法

    公开(公告)号：US07925854B2

    公开(公告)日：2011-04-12

    申请号：US11771241

    申请日：2007-06-29

    申请人： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

    发明人： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

    IPC分类号： G06F12/00

    CPC分类号： G06F13/4239 ,  G11C16/08 ,  G11C16/20 ,  G11C2216/30

    摘要： A memory system architecture is provided in which a memory controller controls memory devices in a serial interconnection configuration. The memory controller has an output port for sending memory commands and an input port for receiving memory responses for those memory commands requisitioning such responses. Each memory device includes a memory, such as, for example, NAND-type flash memory, NOR-type flash memory, random access memory and static random access memory. Each memory command is specific to the memory type of a target memory device. A data path for the memory commands and the memory responses is provided by the interconnection. A given memory command traverses memory devices in order to reach its intended memory device of the serial interconnection configuration. Upon its receipt, the intended memory device executes the given memory command and, if appropriate, sends a memory response to a next memory device. The memory response is transferred to the memory controller.

    摘要翻译： 提供了存储器系统结构，其中存储器控制器控制串行互连配置中的存储器件。 存储器控制器具有用于发送存储器命令的输出端口和用于接收用于请求这样的响应的那些存储器命令的存储器响应的输入端口。 每个存储器件包括诸如NAND型闪存，NOR型闪速存储器，随机存取存储器和静态随机存取存储器之类的存储器。 每个存储器命令特定于目标存储器件的存储器类型。 存储器命令和存储器响应的数据路径由互连提供。 给定的存储器命令遍历存储器件以达到其串行互连配置的预期存储器件。 在其接收时，预期的存储器件执行给定的存储器命令，并且如果适当的话，向下一个存储器件发送存储器响应。 存储器响应被传送到存储器控制器。

    Modular command structure for memory and memory system
    10.
    发明授权
    Modular command structure for memory and memory system 有权
    内存和内存系统的模块化命令结构

    公开(公告)号：US07904639B2

    公开(公告)日：2011-03-08

    申请号：US11840692

    申请日：2007-08-17

    申请人： Jin-Ki Kim ,  HakJune Oh ,  Hong Beom Pyeon

    发明人： Jin-Ki Kim ,  HakJune Oh ,  Hong Beom Pyeon

    IPC分类号： G06F12/00

    CPC分类号： G11C7/1045 ,  G06F13/1678 ,  G11C7/10 ,  Y02D10/14

    摘要： A system including a memory system and a memory controller is connected to a host system. The memory system has at least one memory device storing data. The controller translates the requests from the host system to one or more separatable commands interpretable by the at least one memory device. Each command has a modular structure including an address identifier for one of the at least one memory devices and a command identifier representing an operation to be performed by the one of the at least one memory devices. The at least one memory device and the controller are in a series-connection configuration for communication such that only one memory device is in communication with the controller for input into the memory system. The memory system can include a plurality of memory devices connected to a common bus.

    摘要翻译： 包括存储器系统和存储器控制器的系统连接到主机系统。 存储器系统具有存储数据的至少一个存储器件。 控制器将来自主机系统的请求转换成由至少一个存储设备可解释的一个或多个可分离命令。 每个命令具有模块化结构，其包括用于至少一个存储器设备中的一个的地址标识符和表示由至少一个存储器设备之一执行的操作的命令标识符。 至少一个存储器设备和控制器处于用于通信的串联连接配置中，使得仅一个存储器设备与控制器通信以输入到存储器系统中。 存储器系统可以包括连接到公共总线的多个存储器件。