利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

136 条记录 (耗时 0.036 秒)

    Bridging device having a configurable virtual page size
    1.
    发明授权
    Bridging device having a configurable virtual page size 有权
    桥接设备具有可配置的虚拟页面大小

    公开(公告)号：US08549209B2

    公开(公告)日：2013-10-01

    申请号：US12508926

    申请日：2009-07-24

    申请人： Hong Beom Pyeon ,  Jin-Ki Kim ,  Peter B. Gillingham

    发明人： Hong Beom Pyeon ,  Jin-Ki Kim ,  Peter B. Gillingham

    IPC分类号： G06F13/00

    CPC分类号： G06F12/0238 ,  G06F3/0634 ,  G06F12/04 ,  G06F12/0646 ,  G06F13/36 ,  G06F13/4234 ,  G06F13/4291 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/1087

    摘要： A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. The bridge device has memory organized as banks, where each bank is configured to have a virtual page size that is less than the maximum physical size of the page buffer. Therefore only a segment of data corresponding to the virtual page size stored in the page buffer is transferred to the bank. The virtual page size of the banks is provided in a virtual page size (VPS) configuration command having an ordered structure where the position of VPS data fields containing VPS configuration codes in the command correspond to different banks which are ordered from a least significant bank to a most significant bank. The VPS configuration command is variable in size, and includes only the VPS configuration codes for the highest significant bank being configured and the lower significant banks.

    摘要翻译： 一种复合存储器件，包括分立存储器件和用于控制分立存储器件的桥接器件。 桥接器件具有组织为存储体的存储器，其中每个存储体被配置为具有小于页面缓冲器的最大物理大小的虚拟页面大小。 因此，只有与存储在页面缓冲器中的虚拟页大小相对应的数据段被传送到存储体。 以具有有序结构的虚拟页面大小（VPS）配置命令提供虚拟页面大小，其中在命令中包含VPS配置代码的VPS数据字段的位置对应于从最不重要的银行排序到不同的银行， 最重要的银行。 VPS配置命令的大小是可变的，并且只包括配置的最高有效存储库的VPS配置代码和较低的重要库。

    Bridging device having a frequency configurable clock domain
    2.
    发明授权
    Bridging device having a frequency configurable clock domain 失效
    桥接装置具有频率可配置的时钟域

    公开(公告)号：US08504789B2

    公开(公告)日：2013-08-06

    申请号：US12823472

    申请日：2010-06-25

    申请人： Hong Beom Pyeon ,  Hunsam Jung ,  Peter B. Gillingham

    发明人： Hong Beom Pyeon ,  Hunsam Jung ,  Peter B. Gillingham

    IPC分类号： G06F12/00

    CPC分类号： G06F1/08 ,  G06F3/0676 ,  G06F12/0246 ,  G06F13/1689 ,  G11C7/04

    摘要： A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. A configurable clock controller receives a system clock and generates a memory clock having a frequency that is a predetermined ratio of the system clock. The system clock frequency is dynamically variable between a maximum and a minimum value, and the ratio of the memory clock frequency relative to the system clock frequency is set by loading a frequency register with a Frequency Divide Ratio (FDR) code any time during operation of the composite memory device. In response to the FDR code, the configurable clock controller changes the memory clock frequency.

    摘要翻译： 一种复合存储器件，包括分立存储器件和用于控制分立存储器件的桥接器件。 可配置的时钟控制器接收系统时钟并产生具有系统时钟的预定比率的频率的存储器时钟。 系统时钟频率在最大和最小值之间动态变化，并且存储器时钟频率相对于系统时钟频率的比率通过在运行期间的任何时间加载具有频率分频比（FDR）代码的频率寄存器来设置 复合存储器件。 响应于FDR代码，可配置的时钟控制器改变存储器时钟频率。

    Bridge device architecture for connecting discrete memory devices to a system
    3.
    发明授权
    Bridge device architecture for connecting discrete memory devices to a system 有权
    用于将分立存储器件连接到系统的桥接器件架构

    公开(公告)号：US08363444B2

    公开(公告)日：2013-01-29

    申请号：US13365895

    申请日：2012-02-03

    申请人： Jin-Ki Kim ,  HakJune Oh ,  Hong Beom Pyeon

    发明人： Jin-Ki Kim ,  HakJune Oh ,  Hong Beom Pyeon

    IPC分类号： G11C7/02

    CPC分类号： G11C5/02 ,  G06F13/4234 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1003 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2924/15311

    摘要： A bridge device architecture for connecting discrete memory devices. The bridge device is used in conjunction with a composite memory device including at least one discrete memory device. The bridge device includes a local control interface for connecting to the at least one discrete memory device, a local input/output interface for connecting to the at least one discrete memory device, and a global input/output interface. The global input/output interface receives and provides global memory control signals and also receives and provides write data to and read data from the at least one discrete memory device.

    摘要翻译： 用于连接分立存储器件的桥接器件架构。 桥接器件与包括至少一个分立存储器件的复合存储器件结合使用。 桥接器件包括用于连接至少一个分立存储器件的本地控制接口，用于连接至少一个分立存储器件的本地输入/输出接口以及全局输入/输出接口。 全局输入/输出接口接收并提供全局存储器控制信号，并且还接收并向至少一个离散存储器件提供写入数据和从其读取数据。

    Source side asymmetrical precharge programming scheme
    4.
    发明授权
    Source side asymmetrical precharge programming scheme 有权
    源极不对称预充电编程方案

    公开(公告)号：US08139414B2

    公开(公告)日：2012-03-20

    申请号：US13091479

    申请日：2011-04-21

    申请人： Jin-Ki Kim ,  Hong Beom Pyeon

    发明人： Jin-Ki Kim ,  Hong Beom Pyeon

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/10

    摘要： A method for programming NAND flash cells to minimize program stress while allowing for random page programming operations. The method includes asymmetrically precharging a NAND string from a positively biased source line while the bitline is decoupled from the NAND string, followed by the application of a programming voltage to the selected memory cell, and then followed by the application of bitline data. After asymmetrical precharging and application of the programming voltage, all the selected memory cells will be set to a program inhibit state as they will be decoupled from the other memory cells in their respective NAND strings, and their channels will be locally boosted to a voltage effective for inhibiting programming. A VSS biased bitline will discharge the locally boosted channel to VSS, thereby allowing programming of the selected memory cell to occur. A VDD biased bitline will have no effect on the precharged NAND string, thereby maintaining a program inhibited state of that selected memory cell.

    摘要翻译： 一种用于编程NAND闪存单元以最小化程序压力同时允许随机页面编程操作的方法。 该方法包括从正偏压的源极线不对称地预充电NAND串，同时位线与NAND串解耦，随后将编程电压施加到所选择的存储器单元，然后应用位线数据。 在非对称预充电和编程电压的施加之后，所有选定的存储单元将被设置为编程禁止状态，因为它们将与它们各自的NAND串中的其它存储单元分离，并且它们的通道将被局部升压到有效的电压 用于禁止编程。 VSS偏置位线将本地提升的通道放电到VSS，从而允许对所选存储单元进行编程。 VDD偏置位线对预充电NAND串不起作用，从而保持所选存储单元的程序禁止状态。

    Apparatus and method of page program operation for memory devices with mirror back-up of data
    5.
    发明授权
    Apparatus and method of page program operation for memory devices with mirror back-up of data 失效
    具有镜像备份数据的存储器件的页面编程操作的装置和方法

    公开(公告)号：US08060691B2

    公开(公告)日：2011-11-15

    申请号：US13022166

    申请日：2011-02-07

    申请人： Hong Beom Pyeon ,  Jin-Ki Kim ,  HakJune Oh

    发明人： Hong Beom Pyeon ,  Jin-Ki Kim ,  HakJune Oh

    IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F3/00 ,  G06F5/00

    CPC分类号： G06F13/4243 ,  G06F13/4247

    摘要： An apparatus and method of page program operation is provided. When performing a page program operation with a selected memory device, a memory controller loads the data into the page buffer of one selected memory device and also into the page buffer of another selected memory device in order to store a back-up copy of the data. In the event that the data is not successfully programmed into the memory cells of the one selected memory device, then the memory controller recovers the data from the page buffer of the other memory device. Since a copy of the data is stored in the page buffer of the other memory device, the memory controller does not need to locally store the data in its data storage elements.

    摘要翻译： 提供了一种页面编程操作的装置和方法。 当使用所选择的存储器件执行页面编程操作时，存储器控制器将数据加载到一个所选择的存储器件的页面缓冲器中，并将其加载到另一个选择的存储器件的页面缓冲器中，以便存储数据的备份副本 。 在数据未成功编程到所选存储器件的存储器单元中的情况下，存储器控制器从另一存储器件的页缓冲器中恢复数据。 由于数据的副本存储在另一存储器件的页缓冲器中，所以存储器控制器不需要将数据本地存储在其数据存储元件中。

    Source side asymmetrical precharge programming scheme
    6.
    发明授权
    Source side asymmetrical precharge programming scheme 有权
    源极不对称预充电编程方案

    公开(公告)号：US07952929B2

    公开(公告)日：2011-05-31

    申请号：US12026825

    申请日：2008-02-06

    申请人： Jin-Ki Kim ,  Hong Beom Pyeon

    发明人： Jin-Ki Kim ,  Hong Beom Pyeon

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/10

    摘要： A method for programming NAND flash cells to minimize program stress while allowing for random page programming operations. The method includes asymmetrically precharging a NAND string from a positively biased source line while the bitline is decoupled from the NAND string, followed by the application of a programming voltage to the selected memory cell, and then followed by the application of bitline data. After asymmetrical precharging and application of the programming voltage, all the selected memory cells will be set to a program inhibit state as they will be decoupled from the other memory cells in their respective NAND strings, and their channels will be locally boosted to a voltage effective for inhibiting programming. A VSS biased bitline will discharge the locally boosted channel to VSS, thereby allowing programming of the selected memory cell to occur. A VDD biased bitline will have no effect on the precharged NAND string, thereby maintaining a program inhibited state of that selected memory cell.

    摘要翻译： 一种用于编程NAND闪存单元以最小化程序压力同时允许随机页面编程操作的方法。 该方法包括从正偏压的源极线不对称地预充电NAND串，同时位线与NAND串解耦，随后将编程电压施加到所选择的存储器单元，然后应用位线数据。 在非对称预充电和编程电压的施加之后，所有选定的存储单元将被设置为编程禁止状态，因为它们将与它们各自的NAND串中的其它存储单元分离，并且它们的通道将被局部升压到有效的电压 用于禁止编程。 VSS偏置位线将本地提升的通道放电到VSS，从而允许对所选存储单元进行编程。 VDD偏置位线对预充电NAND串不起作用，从而保持所选存储单元的程序禁止状态。

    Memory with output control
    7.
    发明授权
    Memory with output control 有权
    内存带输出控制

    公开(公告)号：US07515471B2

    公开(公告)日：2009-04-07

    申请号：US11583354

    申请日：2006-10-19

    申请人： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

    发明人： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C2207/107

    摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

    摘要翻译： 公开了一种用于控制向半导体存储器中的串行数据链路接口的输出端口传送数据的装置，系统和方法。 在一个示例中，闪存设备可以具有多个串行数据链路，多个存储器组和控制输入端口，其使得存储器设备能够将串行数据传送到存储器件的串行数据输出端口。 在另一示例中，闪存器件可以具有单个串行数据链路，单个存储体，串行数据输入端口，用于接收输出使能信号的控制输入端口。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。

    APPARATUS AND METHOD FOR PRODUCING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES OF MIXED TYPE
    8.
    发明申请
    APPARATUS AND METHOD FOR PRODUCING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES OF MIXED TYPE 有权
    用于生产混合类型的串联互连设备的设备标识符的装置和方法

    公开(公告)号：US20080181214A1

    公开(公告)日：2008-07-31

    申请号：US11692452

    申请日：2007-03-28

    申请人： Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim ,  Shuji Sumi

    发明人： Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim ,  Shuji Sumi

    IPC分类号： H04L12/56

    CPC分类号： G06F13/4243

    摘要： A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR- and AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) as a packet are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. In a case of no-match, the ID generation is skipped and no ID is generated for another device. The DT is combined with the generated or the received ID depending on the device type match determination. The combined DT and ID is as a packet transferred to a next device. Such a device type match determination and ID generation or skip are performed in all devices of the several interconnection. With reference to device type provided to the interconnected devices, IDs are sequentially generated. The SI containing the DT, the ID and an ID generation command is transmitted in a packet basis to a next device.

    摘要翻译： 多个混合型存储器件（例如，DRAM，SRAM，MRAM以及NAND-，NOR-和AND-型闪存）被串联连接。 每个设备都有其设备类型的设备类型信息。 作为分组的串行输入（SI）中包含的特定设备类型（DT）和设备标识符（ID）被馈送到串行互连的一个设备。 设备确定馈送的DT是否匹配设备的DT。 在匹配的情况下，包含在该设备中的计算器执行计算以生成另一设备的ID，并且将馈送的ID锁存在设备的寄存器中。 在不匹配的情况下，跳过ID生成，并且不为另一设备生成ID。 根据设备类型匹配确定，DT与所生成或接收的ID组合。 组合的DT和ID作为传送到下一个设备的分组。 在多个互连的所有设备中执行这样的设备类型匹配确定和ID生成或跳过。 参考提供给互连设备的设备类型，依次生成ID。 将包含DT，ID和ID生成命令的SI以分组的形式发送到下一个设备。