公开(公告)号：US20190267447A1

公开(公告)日：2019-08-29

申请号：US16410293

申请日：2019-05-13

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Franz-Josef Niedernostheide ,  Christian Philipp Sandow

IPC: H01L29/06 ,  H01L29/739 ,  H01L29/78

Abstract: A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, an active cell field in the body, and a plurality of first and second cells in the active cell field. Each cell is electrically connected to the first load terminal structure and to a drift region. Each first cell includes a mesa having a port region electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each second cell includes a mesa having a port region of the opposite conductivity type electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each mesa is spatially confined in a direction perpendicular to a direction of the load current within the respective mesa, by an insulation structure and has a total extension of less than 100 nm in the direction.

公开(公告)号：US20190109188A1

公开(公告)日：2019-04-11

申请号：US16196373

申请日：2018-11-20

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Franz-Josef Niedernostheide ,  Frank Dieter Pfirsch ,  Christian Philipp Sandow

IPC: H01L29/06 ,  H03K17/567 ,  H01L29/10 ,  H01L29/739 ,  H01L29/08 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/063 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/7394 ,  H01L29/7397 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7813 ,  H01L29/7828 ,  H03K17/567

Abstract: A power semiconductor device is disclosed. The device includes a semiconductor body coupled to a first load terminal structure and a second load terminal structure, a first cell and a second cell. A first mesa is included in the first cell, the first mesa including: a first port region and a first channel region. A second mesa included in the second cell, the second mesa including a second port region. A third cell is electrically connected to the second load terminal structure and electrically connected to a drift region. The third cell includes a third mesa comprising: a third port region, a third channel region, and a third control electrode.

公开(公告)号：US09876004B2

公开(公告)日：2018-01-23

申请号：US15016992

申请日：2016-02-05

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Franz-Josef Niedernostheide ,  Uwe Kellner-Werdehausen ,  Reiner Barthelmess

IPC: H01L27/02 ,  H01L29/36 ,  H01L29/167 ,  H01L21/324 ,  H01L29/861 ,  H01L29/66 ,  H01L29/74 ,  H01L29/06 ,  H01L29/739 ,  H01L29/165 ,  H01L29/08 ,  H01L27/102 ,  H01L29/10

CPC classification number: H01L27/0255 ,  H01L21/324 ,  H01L27/1027 ,  H01L29/0692 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/0839 ,  H01L29/1012 ,  H01L29/1016 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66136 ,  H01L29/66363 ,  H01L29/7395 ,  H01L29/7428 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor component including a short-circuit structure. One embodiment provides a semiconductor component having a semiconductor body composed of doped semiconductor material. The semiconductor body includes a first zone of a first conduction type and a second zone of a second conduction type, complementary to the first conduction type, the second zone adjoining the first zone. The first zone and the second zone are coupled to an electrically highly conductive layer. A connection zone of the second conduction type is arranged between the second zone and the electrically highly conductive layer.

公开(公告)号：US20180006110A1

公开(公告)日：2018-01-04

申请号：US15637459

申请日：2017-06-29

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Franz-Josef Niedernostheide ,  Christian Philipp Sandow

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/739

CPC classification number: H01L29/0634 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/7397 ,  H01L29/7803 ,  H01L29/7813

Abstract: A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, an active cell field in the body, and a plurality of first and second cells in the active cell field. Each cell is electrically connected to the first load terminal structure and to a drift region. Each first cell includes a mesa having a port region electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each second cell includes a mesa having a port region of the opposite conductivity type electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each mesa is spatially confined in a direction perpendicular to a direction of the load current within the respective mesa, by an insulation structure and has a total extension of less than 100 nm in the direction.

公开(公告)号：US09859408B2

公开(公告)日：2018-01-02

申请号：US15331415

申请日：2016-10-21

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Franz-Josef Niedernostheide ,  Christian Philipp Sandow

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/7397 ,  H01L29/0607 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7813

Abstract: A power semiconductor transistor includes a semiconductor body coupled to a load terminal, a drift region, a first trench extending into the semiconductor body and including a control electrode electrically insulated from the semiconductor body by an insulator, a source region arranged laterally adjacent to a sidewall of the first trench and electrically connected to the load terminal, a channel region arranged laterally adjacent to the same trench sidewall as the source region, a second trench extending into the semiconductor body, and a guidance zone electrically connected to the load terminal and extending deeper into the semiconductor body than the first trench. The guidance zone is adjacent the opposite sidewall of the first trench as the source region and adjacent one sidewall of the second trench. In a section arranged deeper than the bottom of the first trench, the guidance zone extends laterally towards the channel region.

公开(公告)号：US09859272B2

公开(公告)日：2018-01-02

申请号：US15210449

申请日：2016-07-14

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Holger Huesken ,  Franz-Josef Niedernostheide ,  Frank Dieter Pfirsch ,  Roman Roth ,  Christian Philipp Sandow ,  Carsten Schaeffer ,  Stephan Voss

IPC: H01L29/66 ,  H01L27/06 ,  H01L29/739 ,  H01L29/10 ,  H01L29/45 ,  H01L29/47 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165

CPC classification number: H01L27/0664 ,  H01L29/0619 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/205 ,  H01L29/45 ,  H01L29/47 ,  H01L29/7397 ,  H01L29/8611 ,  H01L29/8613 ,  H01L29/868 ,  H01L29/872

Abstract: A semiconductor device comprising a source region being electrically connected to a first load terminal (E) of the semiconductor device and a drift region comprising a first semiconductor material (M1) having a first band gap, the drift region having dopants of a first conductivity type and being configured to carry at least a part of a load current between the first load terminal (E) and a second load terminal (C) of the semiconductor device, is presented. The semiconductor device further comprises a semiconductor body region having dopants of a second conductivity type complementary to the first conductivity type and being electrically connected to the first load terminal (E), a transition between the semiconductor body region and the drift region forming a pn-junction, wherein the pn-junction is configured to block a voltage applied between the first load terminal (E) and the second load terminal (C). The semiconductor body region isolates the source region from the drift region and includes a reduced band gap zone comprising a second semiconductor material (M2) having a second band gap that is smaller than the first band gap, wherein the reduced band gap zone is arranged in the semiconductor body region such that the reduced band gap zone and the source region exhibit, in a cross-section along a vertical direction (Z), at least one of a common lateral extension range (LR) along a first lateral direction (X) and a common vertical extension range (VR) along the vertical direction (Z).

公开(公告)号：US09741571B2

公开(公告)日：2017-08-22

申请号：US15081220

申请日：2016-03-25

Applicant: Infineon Technologies AG

Inventor： Roman Baburske ,  Christian Jaeger ,  Franz-Josef Niedernostheide ,  Hans-Joachim Schulze ,  Antonio Vellei

IPC: H01L21/26 ,  H01L21/268 ,  H01L21/04 ,  H01L29/36 ,  H01L29/66 ,  H01L29/739 ,  H01L29/08

CPC classification number: H01L21/268 ,  H01L21/0465 ,  H01L29/0834 ,  H01L29/36 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/861

Abstract: Disclosed is a bipolar semiconductor device, comprising a semiconductor body having a first surface; and a base region of a first doping type and a first emitter region in the semiconductor body, wherein the first emitter region adjoins the first surface and comprises a plurality of first type emitter regions of a second doping type complementary to the first doping type, a plurality of second type emitter regions of the second doping type, a plurality of third type emitter regions of the first doping type, and a recombination region comprising recombination centers, wherein the first type emitter regions and the second type emitter regions extend from the first surface into the semiconductor body, wherein the first type emitter regions have a higher doping concentration and extend deeper into the semiconductor body from the first surface than the second type emitter regions, wherein the third type emitter regions adjoin the first type emitter regions and the second type emitter regions, and wherein the recombination region is located at least in the first type emitter regions and the third type emitter regions.

公开(公告)号：US20170179268A1

公开(公告)日：2017-06-22

申请号：US15449634

申请日：2017-03-03

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Franz-Josef Niedernostheide

IPC: H01L29/739 ,  H01L29/32 ,  H01L29/08 ,  H01L21/266 ,  H01L29/423 ,  H01L29/66 ,  H01L21/265 ,  H01L29/417 ,  H01L21/22

CPC classification number: H01L29/7393 ,  H01L21/221 ,  H01L21/263 ,  H01L21/265 ,  H01L21/266 ,  H01L29/0834 ,  H01L29/167 ,  H01L29/32 ,  H01L29/41708 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7397

Abstract: A method for forming a bipolar semiconductor switch includes providing a semiconductor body which has a main surface, a back surface arranged opposite to the main surface, and a first semiconductor layer, and reducing a charge carrier life-time in the semiconductor body. The charge carrier life-time is reduced by at least one of indiffusing heavy metal into the first semiconductor layer, implanting protons into the first semiconductor layer and implanting helium nuclei into the first semiconductor layer, so that the charge carrier life-time has, in a vertical direction which is substantially orthogonal to the main surface, a minimum in a lower n-type portion of the first semiconductor layer where a concentration of n-type dopants is substantially close to a maximum.

公开(公告)号：US09373710B2

公开(公告)日：2016-06-21

申请号：US14278519

申请日：2014-05-15

Applicant: Infineon Technologies AG

Inventor： Vera Van Treek ,  Frank Pfirsch ,  Roman Baburske ,  Franz-Josef Niedernostheide

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7395 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/7397

Abstract: A semiconductor component is described herein. In accordance with one example of the invention, the semiconductor component includes a semiconductor body, which has a top surface and a bottom surface. A body region, which is doped with dopants of a second doping type, is arranged at the top surface of the semiconductor body. A drift region is arranged under the body region and doped with dopants of a first doping type, which is complementary to the second doping type. Thus a first pn-junction is formed at the transition between the body region and the drift region. A field stop region is arranged under the drift region and adjoins the drift region. The field stop region is doped with dopants of the same doping type as the drift region. However, the concentration of dopants in the field stop region is higher than the concentration of dopants in the drift region. At least one pair of semiconductor layers composed of a first and a second semiconductor layer are arranged in the drift region. The first semiconductor layer extends substantially parallel to the top surface of the semiconductor body and is doped with dopants of the first doping type but with a higher concentration of dopants than the drift region. The second semiconductor layer is arranged adjacent to or adjoining the first semiconductor layer and is doped with dopants of the second doping type. Furthermore, the second semiconductor layer is structured to include openings so that a vertical current path is provided through the drift region without an intervening pn-junction.

Abstract translation: 本文描述了半导体部件。 根据本发明的一个示例，半导体部件包括具有顶表面和底表面的半导体本体。 掺杂有第二掺杂类型的掺杂剂的体区设置在半导体本体的顶表面。 漂移区布置在体区下方并掺杂有与第二掺杂类型互补的第一掺杂类型的掺杂剂。 因此，在身体区域和漂移区域之间的过渡处形成第一pn结。 漂移区域下方设置场停止区域，并与漂移区域相邻。 场停止区域掺杂有与漂移区相同的掺杂类型的掺杂剂。 然而，场停止区域中的掺杂剂的浓度高于漂移区域中的掺杂剂的浓度。 在漂移区域中布置由第一和第二半导体层组成的至少一对半导体层。 第一半导体层基本上平行于半导体本体的顶表面延伸，并掺杂有第一掺杂类型的掺杂剂，但具有比漂移区更高的掺杂剂浓度。 第二半导体层被布置为与第一半导体层相邻或相邻，并且掺杂有第二掺杂类型的掺杂剂。 此外，第二半导体层被构造成包括开口，使得通过漂移区域提供垂直电流路径，而没有中间pn结。

公开(公告)号：US09054151B2

公开(公告)日：2015-06-09

申请号：US14053631

申请日：2013-10-15

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Franz-Josef Niedernostheide ,  Yvonne Gawlina

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/36 ,  H01L29/74 ,  H01L29/78 ,  H01L29/861 ,  H01L21/263 ,  H01L21/265

CPC classification number: H01L29/7393 ,  H01L21/263 ,  H01L21/26506 ,  H01L29/0834 ,  H01L29/36 ,  H01L29/66 ,  H01L29/66333 ,  H01L29/66363 ,  H01L29/74 ,  H01L29/7432 ,  H01L29/78 ,  H01L29/861

Abstract: A semiconductor device includes a semiconductor body including a first surface having a normal direction defining a vertical direction, a first n-type semiconductor region arranged below the first surface and having a first maximum doping concentration and a second n-type semiconductor region arranged below the first n-type semiconductor region and including, in a vertical cross-section, two spaced apart first n-type portions each adjoining the first n-type semiconductor region, having a maximum doping concentration which is higher than the first maximum doping concentration and having a first minimum distance to the first surface, and a second n-type portion adjoining the first n-type semiconductor region, having a maximum doping concentration which is higher than the first maximum doping concentration and a second minimum distance to the first surface which is larger than the first minimum distance. A p-type second semiconductor layer forms a pn-junction with the second n-type portion.

Abstract translation: 半导体器件包括半导体本体，其包括具有限定垂直方向的法线方向的第一表面，布置在第一表面下方并具有第一最大掺杂浓度的第一n型半导体区域和布置在第一表面下方的第二n型半导体区域 第一n型半导体区域，并且在垂直截面中包括两个间隔开的第一n型部分，每个邻近第一n型半导体区域的第一n型部分具有高于第一最大掺杂浓度的最大掺杂浓度，并且具有 与第一表面的第一最小距离以及邻接第一n型半导体区域的第二n型部分，其具有高于第一最大掺杂浓度的最大掺杂浓度和第一最小掺杂浓度的第二最小距离， 大于第一最小距离。 p型第二半导体层与第二n型部分形成pn结。