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    Technologies for demoting cache lines to shared cache
    66.
    发明授权
    Technologies for demoting cache lines to shared cache 有权

    公开(公告)号：US10657056B2

    公开(公告)日：2020-05-19

    申请号：US16024773

    申请日：2018-06-30

    Applicant: Intel Corporation

    Inventor： Eliezer Tamir ,  Bruce Richardson ,  Niall Power ,  Andrew Cunningham ,  David Hunt ,  Kevin Devey ,  Changzheng Wei

    IPC: G06F12/084 ,  G06F12/1072 ,  H04L12/933 ,  G06F12/128 ,  G06F13/28

    Abstract: Technologies for demoting cache lines to a shared cache include a compute device with at least one processor having multiple cores, a cache memory with a core-local cache and a shared cache, and a cache line demote device. A processor core of a processor of the compute device is configured to retrieve at least a portion of data of a received network packet and move the data into one or more core-local cache lines of the core-local cache. The processor core is further configured to perform a processing operation on the data and transmit a cache line demotion command to the cache line demote device subsequent to having completed the processing operation. The cache line demote device is configured to perform a cache line demotion operation to demote the data from the core-local cache lines to shared cache lines of the shared cache. Other embodiments are described herein.

    Techniques for cooperative execution between asymmetric processor cores
    68.
    发明授权
    Techniques for cooperative execution between asymmetric processor cores 有权

    公开(公告)号：US10346175B2

    公开(公告)日：2019-07-09

    申请号：US15425908

    申请日：2017-02-06

    Applicant: Intel Corporation

    Inventor： Eliezer Tamir ,  Ben-Zion Friedman

    IPC: G06F9/38 ,  G06F1/32 ,  G06F9/46 ,  G06F1/329 ,  G06F1/3293 ,  G06F9/50

    Abstract: Various embodiments are generally directed to techniques for cooperation between a higher function core and a lower power core to minimize the effects of interrupts on a current flow of execution of instructions. An apparatus may include a lower power core comprising a first instruction pipeline, the lower power core to stop a first flow of execution in the first instruction pipeline and execute instructions of a handler routine in the first instruction pipeline to perform a first task of handling an interrupt; and a higher function core comprising a second instruction pipeline, the higher function core to, following the performance of the first task, schedule execution of instructions of a second task of handling the interrupt in the second instruction pipeline to follow a second flow of execution in the second instruction pipeline, the first task more time-sensitive than the second task. Other embodiments are described and claimed.

    FLOW BASED RATE LIMIT
    69.
    发明申请
    FLOW BASED RATE LIMIT 审中-公开

    公开(公告)号：US20180322913A1

    公开(公告)日：2018-11-08

    申请号：US15589893

    申请日：2017-05-08

    Applicant: Intel Corporation

    Inventor： Ben-Zion Friedman ,  Eliezer Tamir ,  Manasi Deval

    IPC: G11C11/4076 ,  G06F13/16 ,  G11C8/18 ,  G06F12/06 ,  G06F13/42

    CPC classification number: G11C11/4076 ,  G06F11/00 ,  G06F12/02 ,  G06F12/063 ,  G06F12/0653 ,  G06F13/1626 ,  G06F13/4217 ,  G11C8/00 ,  G11C8/18

    Abstract: Disclosed is a mechanism maintain flow rate limits to flows in a server operating in a single root input/output virtualization (SR-IOV) environment. A transmit pipeline assigns a dedicated transmit queue to a flow. A scheduler allocates a flow transmit bandwidth to the dedicated transmit queue to enforce the flow rate limit. The transmit pipeline assigns the dedicated transmit queue to the flow upon receiving a packet of the flow. A queue identifier (ID) for the dedicated transmit queue is forwarded to a tenant process acting as a source of the flow to support forwarding of packets of the flow to the proper transmit queue. The transmit pipeline maintains security by comparing packet destinations of packets with the destination of the flow associated with the dedicated transmit queue. Packets in the dedicated destination queue with destinations that do not match the flow destination may be dropped.

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