公开(公告)号：US09196707B2

公开(公告)日：2015-11-24

申请号：US14073159

申请日：2013-11-06

Applicant: International Business Machines Corporation

Inventor： Michael P. Chudzik ,  Deleep R. Nair ,  Vijay Narayanan ,  Carl J. Radens ,  Jay M. Shah

IPC: H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/283 ,  H01L29/78

CPC classification number: H01L29/66575 ,  H01L21/28017 ,  H01L21/283 ,  H01L21/823864 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/78

Abstract: At least one layer including a scavenging material and a dielectric material is deposited over a gate stack, and is subsequently anisotropically etched to form a oxygen-scavenging-material-including gate spacer. The oxygen-scavenging-material-including gate spacer can be a scavenging-nanoparticle-including gate spacer or a scavenging-island-including gate spacer. The scavenging material is distributed within the oxygen-scavenging-material-including gate spacer in a manner that prevents an electrical short between a gate electrode and a semiconductor material underlying a gate dielectric. The scavenging material actively scavenges oxygen that diffuses toward the gate dielectric from above, or from the outside of, a dielectric gate spacer that can be formed around the oxygen-scavenging-material-including gate spacer.

Abstract translation: 包括清除材料和电介质材料的至少一层沉积在栅叠层上，随后进行各向异性蚀刻以形成含氧清除材料的栅间隔物。 含氧清除材料的栅极间隔物可以是包含清除纳米颗粒的栅极间隔物或含有扫气岛的栅极间隔物。 清除材料以防止栅极电极和栅极电介质下方的半导体材料之间的电短路的方式分布在含氧清除材料的栅极间隔物内。 清扫材料主动地清除从可以形成在含氧清除材料的栅极间隔物周围形成的介电栅极隔离物的上方或外部扩散到栅极电介质的氧。

公开(公告)号：US09147031B2

公开(公告)日：2015-09-29

申请号：US13755726

申请日：2013-01-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Carl J. Radens ,  Amith Singhee

IPC: G06F17/50 ,  G11C29/56

CPC classification number: G06F17/5081 ,  G06F17/5036 ,  G06F2217/10 ,  G11C29/56008

Abstract: Systems and methods for determining a chip yield are disclosed. One system includes a first level integration solver and a second level integration solver. The first level integration solver is configured to obtain a first probability distribution function modeling variations within a chip and to perform a discontinuous first level integration with the first probability distribution function. In addition, the second level integration solver is implemented by a hardware processor and is configured to perform a continuous second level integration based on a second probability distribution function modeling variations between dies to determine the chip yield.

Abstract translation: 公开了用于确定芯片产量的系统和方法。 一个系统包括第一级积分求解器和第二级积分求解器。 第一级积分求解器被配置为获得对芯片内的变化进行建模的第一概率分布函数，并执行与第一概率分布函数的不连续的第一级积分。 此外，第二级集成解算器由硬件处理器实现，并且被配置为基于模具之间的变化建模的第二概率分布函数来执行连续的第二级集成以确定芯片产量。

公开(公告)号：US20150200276A1

公开(公告)日：2015-07-16

申请号：US14156489

申请日：2014-01-16

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L27/0886 ,  H01L29/66818

Abstract: After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process.

Abstract translation: 在半导体散热片上形成栅极结构之后，在形成凸起的有源区之前，使用定向离子束在半导体鳍片的端壁上形成与半导体鳍片的长度方向垂直的绝缘材料部分。 方向离子束的角度选择为包括半导体鳍片的长度方向的垂直平面，从而避免在半导体鳍片的纵向侧壁上形成电介质材料部分。 执行半导体材料的选择性外延以从半导体鳍片的侧壁表面生长凸起的有源区域。 可选地，可以在选择性外延工艺之前去除电介质材料部分的水平部分。 此外，可以在选择性外延工艺之后任选地去除电介质材料部分。

公开(公告)号：US09040369B2

公开(公告)日：2015-05-26

申请号：US13752567

申请日：2013-01-29

Applicant: International Business Machines Corporation

Inventor： Shahab Siddiqui ,  Michael P. Chudzik ,  Carl J. Radens

IPC: H01L21/338 ,  H01L29/66 ,  H01L21/28 ,  H01L21/768 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/66575 ,  H01L21/28088 ,  H01L21/76897 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: The present disclosure provides a method for forming a semiconductor device that includes forming a replacement gate structure overlying a channel region of a substrate. A mandrel dielectric layer is formed overlying source and drain regions of the substrate. The replacement gate structure is removed to provide an opening exposing the channel region of the substrate. A functional gate structure is formed over the channel region including a work function metal layer. A protective cap structure is formed over the functional gate structure. At least one via is etched through the mandrel dielectric layer selective to the protective cap structure to expose a portion of at least one of the source region and the drain region. A conductive fill is then formed in the vias to provide a contact to the at least one of the source region and the drain region.

Abstract translation: 本公开提供了一种用于形成半导体器件的方法，其包括形成覆盖在衬底的沟道区上的替代栅极结构。 在衬底的源极和漏极区域上形成心轴介电层。 去除替代栅极结构以提供暴露衬底的沟道区的开口。 在包括功函数金属层的沟道区域上形成功能栅极结构。 在功能栅极结构上形成保护帽结构。 通过对保护盖结构有选择性的心轴介质层蚀刻至少一个通孔，以暴露源极区域和漏极区域中的至少一个的一部分。 然后在通孔中形成导电填充物以提供与源极区域和漏极区域中的至少一个的接触。

公开(公告)号：US20150004802A1

公开(公告)日：2015-01-01

申请号：US14487213

申请日：2014-09-16

Applicant: International Business Machines Corporation

Inventor： Deok-kee Kim ,  Kenneth T. Settlemyer, JR. ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Dirk Pfeiffer ,  Timothy J. Dalton ,  Katherina E. Babich ,  Arpan P. Mohorowala ,  Harald Okorn-Schmidt

IPC: H01L21/033

CPC classification number: H01L21/0337 ,  G03F7/11 ,  H01L21/027 ,  H01L21/0332 ,  H01L21/0334 ,  H01L21/0338 ,  H01L21/31144

Abstract: Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.

Abstract translation: 增加对芯片区域的保护是通过在半导体制造工艺方面具有增强的鲁棒性的掩模结构来提供的，或者可以以相对于下面的材料或两者的增加的选择性和可控性被去除。 提供掩模结构，其显示化学反应，颗粒或材料类型的界面，其可被利用以增强任一种或两种类型的保护。 这种掩模的结构包括TERA材料，其可以使用氟化氢和吸湿性酸或有机溶剂的混合物以及相似或不同材料的两层结构进行转化或水合并选择性蚀刻。

公开(公告)号：US08670281B2

公开(公告)日：2014-03-11

申请号：US13915913

申请日：2013-06-12

Applicant: International Business Machines Corporation

Inventor： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Jente B. Kuang ,  Carl J. Radens

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G11C7/02 ,  G11C7/04 ,  G11C11/417 ,  G11C11/419

Abstract: An apparatus and method for combating the effects of bias temperature instability (BTI) and other variability in a memory cell. Bit lines connecting to a memory cell contain two alternate paths that criss-cross to connect a lower portion of a first bit line to an upper portion of a second bit line, and to connect a lower portion of the second bit line to an upper portion of the first bit line. Alternative to activating transistors on the bit lines to read and write to the memory cell, transistors on the alternative paths may be activated to read and write to the memory cell from the opposite bit line. In this fashion, the memory cell may be read through the bit lines to a sense amplifier where the bit values are latched. While the bit values remain latched in the sense amplifier, the transistors on the bit lines are deactivated and the transistors on the alternate paths are activated. When the word line is accessed, the bit values will be written into the opposite sides of the memory cell, reversing the biases.

Abstract translation: 用于抵抗偏置温度不稳定性（BTI）和存储器单元中其他变异性的影响的装置和方法。 连接到存储单元的位线包含两个交替的交叉路径，其交叉连接第一位线的下部与第二位线的上部，并且将第二位线的下部连接到上部 的第一个位线。 在位线上激活晶体管以读取和写入存储器单元的替代方案是替代路径上的晶体管可被激活以从相对位线读取和写入存储器单元。 以这种方式，存储器单元可以通过位线读取到其中位值被锁存的读出放大器。 当位值保持锁存在读出放大器中时，位线上的晶体管被​​去激活，并且备用路径上的晶体管被​​激活。 当访问字线时，位值将写入存储单元的相对侧，反转偏置。