公开(公告)号：US20240280899A1

公开(公告)日：2024-08-22

申请号：US18112803

申请日：2023-02-22

Applicant: International Business Machines Corporation

Inventor： Rudy J. Wojtecki ,  Nelson Felix ,  Krystelle Lionti ,  Noel Arellano

IPC: G03F7/004 ,  G03F7/16 ,  G03F7/20

CPC classification number: G03F7/0045 ,  G03F7/165 ,  G03F7/2016

Abstract: A surfactant or photoacid generator (PAG) that forms a self-assembled monolayer is deposited on a substrate surface. Application of electron beam (e-beam) and/or extreme ultraviolet (EUV) radiation to the substrate surface forms a negative or positive tone pattern on the monolayer. A hydroxamic acid may be used to form a negative tone self-assembled monolayer and a silane or PAG may be used to form a positive tone self-assembled monolayer. Area selective deposition of an EUV absorbing material on the negative or positive tone patterned monolayer forms a negative or positive tone EUV absorbing mask, respectively.

公开(公告)号：US20240222448A1

公开(公告)日：2024-07-04

申请号：US18148577

申请日：2022-12-30

Applicant: International Business Machines Corporation

Inventor： Eric Miller ,  Nelson Felix ,  Andrew Herbert Simon

IPC: H01L29/417 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/76831 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes first and second nanosheet stacks above an upper surface of a semiconductor substrate, a first source/drain on an end of the first nanosheet stack, and a second source/drain on an end of the second nanosheet stack. A first gate stack wraps around individual channels of the first nanosheet stack and a second gate stack wraps around individual channels the second nanosheet stack. An interlayer dielectric covers the first and second nanosheet stacks, the first and second source/drains, and the first and second gate stacks. The semiconductor device further includes a first source/drain contact that contacts the first source/drain and a second source/drain contact that contacts the second source/drain. The first and second source/drain contacts extend continuously from the first and second source/drains, respectively, to an upper surface of the interlayer dielectric.

公开(公告)号：US12019376B2

公开(公告)日：2024-06-25

申请号：US17507933

申请日：2021-10-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jing Guo ,  Bharat Kumar ,  Ekmini A. De Silva ,  Jennifer Church ,  Dario Goldfarb ,  Nelson Felix

IPC: H01L21/027 ,  G03F7/20 ,  G03F7/32

CPC classification number: G03F7/2004 ,  G03F7/322 ,  G03F7/325

Abstract: A method of making an adhesion layer of an extreme ultraviolet (EUV) stack is presented. The method includes grafting an ultraviolet (UV) sensitive polymer brush on a hardmask, the polymer brush including a UV cleavable unit, depositing EUV resist over the polymer brush, exposing the EUV resist to remove the EUV resist in exposed areas by applying a developer, and flooding the exposed area with a UV light and a solvent developer to remove exposed portions of the polymer brush.

公开(公告)号：US11699592B2

公开(公告)日：2023-07-11

申请号：US17467428

申请日：2021-09-06

Applicant: International Business Machines Corporation

Inventor： Nelson Felix ,  Ekmini Anuja De Silva ,  Praveen Joseph ,  Ashim Dutta

IPC: H01L21/308 ,  H01L21/033

CPC classification number: H01L21/3086 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3088

Abstract: An initial semiconductor structure includes an underlying substrate, a hard mask stack, an organic planarization layer (OPL), a first complementary material, and a patterned photoresist layer patterned into a plurality of photoresist pillars defining a plurality of photoresist trenches. The first material is partially etched inward of the trenches, to provide trench regions, and the photoresist is removed. The trench regions are filled with a second complementary material, preferentially etchable with respect to the first material. A polymer brush is grafted on the second material but not the first material, to form polymer brush regions with intermediate regions not covered by the brush. The first material is anisotropically etched the at the intermediate regions but not the brush regions. The OPL is etched inward of the intermediate regions, to provide a plurality of OPL pillars defining a plurality of OPL trenches inverted with respect to the photoresist pillars.

公开(公告)号：US11695059B2

公开(公告)日：2023-07-04

申请号：US17518649

申请日：2021-11-04

Applicant: International Business Machines Corporation

Inventor： Tao Li ,  Indira Seshadri ,  Nelson Felix ,  Eric Miller

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/66666 ,  H01L21/823814 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/7827

Abstract: A technique relates to a semiconductor device. A first epitaxial material is formed under a bottom surface of a set of fins, the first epitaxial material being under fin channel regions of the set of fins. A second epitaxial material is formed adjacent to the first epitaxial material and remote from the fin channel regions, a combination of the first epitaxial material and the second epitaxial material forming a bottom source or drain (source/drain) layer. A top source/drain layer is formed on an upper portion of the set of fins, gate material being disposed around the set of fins between the top source/drain layer and the bottom source/drain layer.

公开(公告)号：US11682558B2

公开(公告)日：2023-06-20

申请号：US17481981

申请日：2021-09-22

Applicant: International Business Machines Corporation

Inventor： Chi-Chun Liu ,  Ashim Dutta ,  Nelson Felix ,  Ekmini Anuja De Silva

IPC: H01L21/311 ,  H01L21/033

CPC classification number: H01L21/0337 ,  H01L21/31111

Abstract: A semiconductor structure includes a set of mandrel lines and a set of non-mandrel lines disposed on a hardmask in an alternating pattern. Spacers are disposed between adjacent mandrel lines and non-mandrel lines. The spacers include a composition which exhibits an etch rate greater than an etch rate of the mandrel lines and the non-mandrel lines.

公开(公告)号：US11681213B2

公开(公告)日：2023-06-20

申请号：US16282005

申请日：2019-02-21

Applicant: International Business Machines Corporation

Inventor： Nelson Felix ,  Luciana Meli Thompson ,  Ashim Dutta ,  Ekmini A. De Silva

IPC: G03F7/075 ,  G03F1/22 ,  H01L21/308

CPC classification number: G03F1/22 ,  G03F7/0757 ,  H01L21/3081

Abstract: Techniques for EUV resist pattern transfer using a graded hardmask are provided. In one aspect, a method of patterning is provided. The method includes: forming a graded hardmask on a device stack; depositing a resist onto the graded hardmask; patterning the resist to form a pattern in the resist having at least one feature; modifying at least one surface region to increase an etch rate of the graded hardmask; transferring the pattern from the resist to the graded hardmask; and transferring the pattern from the graded hardmask to at least one underlying layer of the device stack. A device structure formed by the patterning method is also provided.

公开(公告)号：US11195995B2

公开(公告)日：2021-12-07

申请号：US16735020

申请日：2020-01-06

Applicant: International Business Machines Corporation

Inventor： Chi-Chun Liu ,  Yann Mignot ,  Ekmini Anuja De Silva ,  Nelson Felix ,  John Christopher Arnold

IPC: H01L43/12 ,  H01L43/02 ,  H01L27/22

Abstract: A method of forming a semiconductor structure includes forming a memorization layer over a substrate, forming a first self-aligned double patterning (SADP) stack including a first organic planarization layer (OPL), masking layer, set of mandrels, and set of spacers, and forming a patterned memorization layer by transferring a first pattern of the first set of spacers to the memorization layer. The method also includes forming a second SADP stack comprising a second OPL, masking layer, set of mandrels, and set of spacers, and forming an array of pillars by transferring a second pattern of the second set of spacers to the patterned memorization layer. The first and second OPL and the first and second sets of mandrels are a spin-on coated OPL material, and the memorization layer and first and second masking layers are a material configured for removal selective to the spin-on coated OPL material.

公开(公告)号：US11177130B2

公开(公告)日：2021-11-16

申请号：US16404312

申请日：2019-05-06

Applicant: International Business Machines Corporation

Inventor： Ekmini Anuja De Silva ,  Dario Goldfarb ,  Nelson Felix ,  Daniel Corliss ,  Rudy J. Wojtecki

IPC: H01L21/027 ,  H01L21/033 ,  G03F7/26 ,  G03F7/20 ,  G03F7/09 ,  H01L21/3213 ,  H01L21/308 ,  G03F7/11 ,  H01L43/12 ,  G03F7/004

Abstract: A lithographic patterning method includes forming a multi-layer patterning material film stack on a semiconductor substrate, the patterning material film stack including a resist layer formed over one or more additional layers, and forming a metal-containing top coat over the resist layer. The method further includes exposing the multi-layer patterning material film stack to patterning radiation through the metal-containing top coat to form a desired pattern in the resist layer, removing the metal-containing top coat, developing the pattern formed in the resist layer, etching at least one underlying layer in accordance with the developed pattern, and removing remaining portions of the resist layer. The metal-containing top coat can be formed, for example, by atomic layer deposition or spin-on deposition over the resist layer, or by self-segregation from the resist layer.

公开(公告)号：US11037786B2

公开(公告)日：2021-06-15

申请号：US16404404

申请日：2019-05-06

Applicant: International Business Machines Corporation

Inventor： Ekmini Anuja De Silva ,  Dario Goldfarb ,  Nelson Felix ,  Daniel Corliss ,  Rudy J. Wojtecki

IPC: H01L21/027 ,  H01L21/033 ,  G03F7/26 ,  G03F7/20 ,  G03F7/09 ,  H01L21/3213 ,  H01L21/308 ,  G03F7/11 ,  H01L43/12

Abstract: A semiconductor structure includes a semiconductor substrate and a multi-layer patterning material film stack formed on the semiconductor substrate. The patterning material film stack includes a resist layer formed over one or more additional layers. The semiconductor structure further includes a metal-containing top coat formed over the resist layer. The metal-containing top coat can be formed, for example, by atomic layer deposition or spin-on deposition over the resist layer, or by self-segregation from the resist layer.