公开(公告)号：US11307250B2

公开(公告)日：2022-04-19

申请号：US16559589

申请日：2019-09-03

Applicant: International Business Machines Corporation

Inventor： Franco Stellari ,  Peilin Song

IPC: G01R31/311

Abstract: A Scanning Time-Resolved Emission (S-TRE) microscope or system includes an optical system configured to collect light from emissions of light generated by a device under test (DUT). A scanning system is configured to permit the emissions of light to be collected from positions across the DUT in accordance with a scan pattern. A timing photodetector is configured to detect a single photon or photons of the emissions of light from the particular positions across the DUT such that the emissions of light are correlated to the positions to create a time-dependent map of the emissions of light across the DUT. The scanning system is configured to update the time-dependent map of the emissions based on combinations of the emissions of light at certain locations.

公开(公告)号：US11061063B2

公开(公告)日：2021-07-13

申请号：US16422411

申请日：2019-05-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Raphael P. Robertazzi ,  Peilin Song ,  Franco Stellari

IPC: G01R31/26 ,  G01R31/30 ,  G01R31/27 ,  G01R31/28 ,  G01R31/311

Abstract: A method for characterizing an integrated circuit that selecting at least two devices from an integrated circuit for measuring light emission, wherein each of the at least two devices have experienced a different level of stress, applying power to the integrated circuit, and measuring the light emission from the at least two devices. The method also includes comparing the light emission that is measured from the at least two devices, wherein a difference between the light emission that is measured from the at least two devices greater than a predetermined ratio indicates that at least one of the devices from the at least two devices has a below specification performance.

公开(公告)号：US20210063716A1

公开(公告)日：2021-03-04

申请号：US16559594

申请日：2019-09-03

Applicant: International Business Machines Corporation

Inventor： Franco Stellari ,  Peilin Song

IPC: G02B21/00 ,  G01J3/443

Abstract: A Scanning Time-Resolved Emission (S-TRE) microscope or system includes an optical system configured to collect light from emissions of light generated by a device under test (DUT). A scanning system is configured to permit the emissions of light to be collected from positions across the DUT in accordance with a scan pattern. A timing photodetector is configured to detect a single photon or photons of the emissions of light from the particular positions across the DUT such that the emissions of light are correlated to the positions to create a time-dependent map of the emissions of light across the DUT. The scanning system is configured to updated the time-dependent map of the emissions based on a transformation of an underlying time-resolved waveform at certain intervals and corresponding to at least one location and generating a pseudo image of the DUT.

公开(公告)号：US10571520B2

公开(公告)日：2020-02-25

申请号：US15590617

申请日：2017-05-09

Applicant: International Business Machines Corporation

Inventor： Dzmitry S. Maliuk ,  Franco Stellari ,  Alan J. Weger ,  Peilin Song

IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/3185 ,  G01R31/317

Abstract: A scan chain latch circuit, a method of operating a latch circuit in a scan chain, and a computer-readable medium having stored thereon a data structure defining a scan chain latch circuit for instantiation on a semiconductor die are disclosed. In an embodiment, the scan chain latch circuit comprises a first latch for holding one data value, a second latch for holding another data value, and a multiplexor. The one data value is applied to a first data input of the multiplexor and the another data value is applied to a second data input of the multiplexor. An alternating clock signal is applied to a select input of the multiplexor to control the output of the multiplexor, wherein the output of the multiplexor toggles between the two data values held in the two latches at a defined frequency.

公开(公告)号：US10379152B2

公开(公告)日：2019-08-13

申请号：US15093190

申请日：2016-04-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Raphael P. Robertazzi ,  Peilin Song ,  Franco Stellari

IPC: G01R31/02 ,  G01R31/26 ,  G01R31/30 ,  G01R31/27 ,  G01R31/28 ,  G01R31/311

Abstract: A method for characterizing an integrated circuit that includes ramping the supply voltage to an integrated circuit as a function of time for each of the transistors in the integrated circuit, and measuring a power supply current for the integrated circuit during the ramping of the power supply voltage. The measured peaks in the power supply current are a current pulse that identifies an operation state in which each of the transistors are in an on state. The peaks in the power supply current are compared to the reference peaks for the power supply current for a reference circuit having a same functionality as the integrated circuit to determine the integrated circuit's fitness.

公开(公告)号：US20180330038A1

公开(公告)日：2018-11-15

申请号：US15842639

申请日：2017-12-14

Applicant: International Business Machines Corporation

Inventor： Andrea Bahgat Shehata ,  Peilin Song ,  Franco Stellari

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/2705 ,  G06F17/50 ,  G06F17/5045 ,  G06F21/14

Abstract: Techniques facilitating integrated circuit identification and reverse engineering are provided. A computer-implemented method can comprise identifying, by a system operatively coupled to a processor, an element within a first elementary cell of one or more elementary cells of an integrated circuit. The method can also comprise matching, by the system, the element with respective elements across the one or more elementary cells including the first elementary cell. The respective elements can be replicas of the element. Further, matching the element with respective elements can be based on a layout analysis of the integrated circuit.

公开(公告)号：US20180322025A1

公开(公告)日：2018-11-08

申请号：US16035032

申请日：2018-07-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Keith A. Jenkins ,  Barry P. Linder ,  Emily A. Ray ,  Raphael P. Robertazzi ,  Peilin Song ,  James H. Stathis ,  Kevin G. Stawiasz ,  Franco Stellari ,  Alan J. Weger ,  Emmanuel Yashchin

IPC: G06F11/22 ,  G06F11/24 ,  G06F11/00

CPC classification number: G06F11/2236 ,  G06F11/008 ,  G06F11/2273 ,  G06F11/24 ,  G06F11/263

Abstract: A method and system are provided for chip testing. The method includes selectively deploying a chip for future use or discarding the chip to prevent the future use, responsive to a stress history of the chip determined using a non-destructive test procedure. The test procedure includes ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto. The test procedure further includes ranking each of the plurality of patterns based on at least one preceding available pattern to provide a plurality of pattern ranks. The test procedure also includes calculating a sum by summing the plurality of pattern ranks. The sum calculated during an initial performance of the test procedure is designated as a baseline, and the sum calculated during a subsequent performance of the test procedure is compared to a threshold derived from the baseline to determine the stress history of the chip.

公开(公告)号：US20180248555A1

公开(公告)日：2018-08-30

申请号：US15445587

申请日：2017-02-28

Applicant: International Business Machines Corporation

Inventor： Keith A. Jenkins ,  Peilin Song ,  James H. Stathis ,  Franco Stellari

IPC: H03L1/00 ,  H03K3/03

CPC classification number: H03L1/00 ,  G01R31/2824 ,  G01R31/2851 ,  H03B1/00 ,  H03B5/12 ,  H03B5/1215 ,  H03B5/30 ,  H03B5/36 ,  H03K3/0315 ,  H04L9/3278

Abstract: An electronic apparatus for testing an integrated circuit (IC) that includes a ring oscillator is provided. The apparatus configures the ring oscillator to produce oscillation at a first frequency and configures the ring oscillator to produce oscillation at a second frequency. The apparatus then compares the second frequency with an integer multiple of the first frequency to determine a resistive voltage drop between a voltage applied to the IC and a local voltage at the ring oscillator. The ring oscillator has a chain of inverting elements forming a long ring and a short ring. The ring oscillator also has an oscillation selection circuit that is configured to disable the short ring so that the ring oscillator produces a fundamental oscillation based on signal propagation through the long ring and enable the short ring so that the ring oscillator produces a harmonic oscillation based on a signal propagation through the short ring and the long ring.

公开(公告)号：US09939486B2

公开(公告)日：2018-04-10

申请号：US15403462

申请日：2017-01-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jifeng Chen ,  Dirk Pfeiffer ,  Thomas M. Shaw ,  Peilin Song ,  Franco Stellari

IPC: G01R31/28 ,  G01R31/311

CPC classification number: G01R31/2855 ,  G01R31/281 ,  G01R31/2817 ,  G01R31/2858 ,  G01R31/2879 ,  G01R31/311

Abstract: Methods for reliability testing include applying a stress voltage to a device under test (DUT); measuring a leakage current across the DUT; triggering measurement of optical emissions from the DUT based on the timing of the measurement of the leakage current; and correlating measurements of the leakage current with measurements of the optical emissions to determine a time and location of a defect occurrence within the DUT by locating instances of increased noise in the leakage current that correspond in time with instances of increased optical emissions.

公开(公告)号：US09874601B2

公开(公告)日：2018-01-23

申请号：US15258535

申请日：2016-09-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jifeng Chen ,  Dirk Pfeiffer ,  Thomas M. Shaw ,  Peilin Song ,  Franco Stellari

IPC: G01R31/28 ,  G01R31/311

CPC classification number: G01R31/2855 ,  G01R31/281 ,  G01R31/2817 ,  G01R31/2858 ,  G01R31/2879 ,  G01R31/311

Abstract: Systems for reliability testing include a picometer configured to measure a leakage current across a device under test (DUT); a camera configured to measure optical emissions from the DUT based on a timing of the measurement of the leakage current; and a test system configured to apply a stress voltage to the DUT and to correlate the leakage current with the optical emissions using a processor to determine a time and location of a defect occurrence within the DUT by locating instances of increased noise in the leakage current that correspond in time with instances of increased optical emissions.