公开(公告)号：US20170309519A1

公开(公告)日：2017-10-26

申请号：US15649182

申请日：2017-07-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Martin M. Frank ,  Renee T. Mo ,  Vijay Narayanan

IPC: H01L21/8258 ,  H01L29/20 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8252 ,  H01L29/51 ,  H01L29/16

Abstract: Semiconductor devices and methods of forming the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region. The second semiconductor region is formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A semiconductor cap is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.

公开(公告)号：US20170243867A1

公开(公告)日：2017-08-24

申请号：US15051790

申请日：2016-02-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Martin M. Frank ,  Renee T. Mo ,  Vijay Narayanan ,  John Rozen

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/8258 ,  H01L27/092

Abstract: Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A nitrogen-containing layer is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.

公开(公告)号：US09646886B1

公开(公告)日：2017-05-09

申请号：US14984471

申请日：2015-12-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Vijay Narayanan ,  John Rozen

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/8234 ,  H01L29/51 ,  H01L21/28 ,  H01L21/02 ,  H01L27/088 ,  H01L29/20 ,  H01L29/49

CPC classification number: H01L21/28035 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/3003 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/8258 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/20 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: Disclosed is a process of making field-effect transistor gate stacks containing different deposited thin film silicon material layers having different hydrogen content, and devices comprising these gate stacks. The threshold voltage (Vt) can be tuned by tailoring the hydrogen content of the thin film silicon material layer positioned below a core dielectric and directly on a semiconductor material substrate.

公开(公告)号：US09634116B2

公开(公告)日：2017-04-25

申请号：US15058512

申请日：2016-03-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Barry P. Linder ,  Vijay Narayanan

IPC: H01L21/338 ,  H01L29/66 ,  H01L21/28 ,  H01L21/30 ,  H01L29/49 ,  H01L21/285 ,  H01L21/306 ,  H01L21/324 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/3003 ,  H01L21/30625 ,  H01L21/324 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of fabricating a gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over an area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; annealing the replacement gate structure in an ambient atmosphere containing hydrogen; and depositing a gap fill layer.

公开(公告)号：US20170092501A1

公开(公告)日：2017-03-30

申请号：US14962093

申请日：2015-12-08

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Martin M. Frank ,  Vijay Narayanan ,  John Rozen

IPC: H01L21/28 ,  H01L21/02

CPC classification number: H01L29/401 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/28158 ,  H01L21/32105 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/66757 ,  H01L29/66795

Abstract: A method for forming a layer of material on a silicon layer comprises depositing a layer of silicon material having a hydrophobic H-terminated surface on a substrate, forming a hydrophilic seed layer on the surface of the silicon material, and depositing an oxide material layer on the hydrophilic seed layer.

公开(公告)号：US09472553B1

公开(公告)日：2016-10-18

申请号：US15093232

申请日：2016-04-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Martin M. Frank ,  Pranita Kerber ,  Vijay Narayanan

IPC: H01L27/092 ,  H01L29/161 ,  H01L29/20 ,  H01L29/49 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/28255 ,  H01L21/28264 ,  H01L21/823842 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/201 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: An electrical device that includes a substrate including a first region of a type III-V semiconductor material and a second region of a type IV germanium containing semiconductor material. An n-type planar FET is present in the first region of the substrate. A p-type planar FET is present in a second region of the substrate. A gate structure for each of the n-type planar FET and the p-type planar FET includes a metal containing layer including at least one of titanium and aluminum atop a high-k gate dielectric. An effective work function of the gate structure for both the n-type and p-type planar FETs is a less than a mid gap of silicon.

公开(公告)号：US20160133753A1

公开(公告)日：2016-05-12

申请号：US14994821

申请日：2016-01-13

Applicant: International Business Machines Corporation

Inventor： Catherine A. Dubourdieu ,  Martin M. Frank ,  Vijay Narayanan

IPC: H01L29/78

CPC classification number: H01L29/78391 ,  H01L21/28088 ,  H01L21/28291 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6684

Abstract: Semiconductor devices are provided such as, ferroelectric transistors and floating gate transistors, that include an epitaxial perovskite/doped strontium titanate structure formed above a surface of a semiconductor substrate. The epitaxial perovskite/doped strontium titanate structure includes a stack of, in any order, a doped strontium titanate and a perovskite type oxide.

公开(公告)号：US20160126145A1

公开(公告)日：2016-05-05

申请号：US14992739

申请日：2016-01-11

Applicant: International Business Machines Corporation ,  Global Foundries Inc

Inventor： Takashi Ando ,  Changhwan Choi ,  Kisik Choi ,  Vijay Narayanan

IPC: H01L21/8238 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L21/823842 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28229 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A replacement metal gate process in which a high-k dielectric is applied. The high-k dielectric may be doped with lanthanum in an NMOS region or aluminum in a PMOS region. A dummy gate structure may be formed over the high-k dielectric and etched to form an opening over the NMOS region and an opening over the PMOS region. Thereafter, first work function metals are deposited in the NMOS opening and second work function metals are applied in the PMOS openings. A suitable gate electrode material may then fill the remainder of the NMOS and PMOS openings.

Abstract translation: 其中施加高k电介质的替代金属栅极工艺。 高k电介质可以在NMOS区域中掺杂镧或在PMOS区域中掺杂铝。 可以在高k电介质上形成伪栅极结构，并被蚀刻以在NMOS区域上形成开口，并且在PMOS区域上形成开口。 此后，第一功函数金属沉积在NMOS开口中，第二功函数金属被施加在PMOS开口中。 合适的栅极材料可以填充NMOS和PMOS开口的其余部分。

公开(公告)号：US09299799B2

公开(公告)日：2016-03-29

申请号：US14300835

申请日：2014-06-10

Applicant: International Business Machines Corporation

Inventor： Catherine A. Dubourdieu ,  Martin M. Frank ,  Vijay Narayanan

IPC: H01L29/51 ,  H01L29/49 ,  H01L21/28

CPC classification number: H01L29/78391 ,  H01L21/28088 ,  H01L21/28291 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6684

Abstract: Semiconductor devices are provided such as, ferroelectric transistors and floating gate transistors, that include an epitaxial perovskite/doped strontium titanate structure formed above a surface of a semiconductor substrate. The epitaxial perovskite/doped strontium titanate structure includes a stack of, in any order, a doped strontium titanate and a perovskite type oxide.

Abstract translation: 提供了诸如铁电晶体管和浮栅晶体管的半导体器件，其包括在半导体衬底的表面上形成的外延钙钛矿/掺杂钛酸锶结构。 外延钙钛矿/掺杂的钛酸锶结构包括以任何顺序的掺杂的钛酸锶和钙钛矿型氧化物的叠层。

公开(公告)号：US09196707B2

公开(公告)日：2015-11-24

申请号：US14073159

申请日：2013-11-06

Applicant: International Business Machines Corporation

Inventor： Michael P. Chudzik ,  Deleep R. Nair ,  Vijay Narayanan ,  Carl J. Radens ,  Jay M. Shah

IPC: H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/283 ,  H01L29/78

CPC classification number: H01L29/66575 ,  H01L21/28017 ,  H01L21/283 ,  H01L21/823864 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/78

Abstract: At least one layer including a scavenging material and a dielectric material is deposited over a gate stack, and is subsequently anisotropically etched to form a oxygen-scavenging-material-including gate spacer. The oxygen-scavenging-material-including gate spacer can be a scavenging-nanoparticle-including gate spacer or a scavenging-island-including gate spacer. The scavenging material is distributed within the oxygen-scavenging-material-including gate spacer in a manner that prevents an electrical short between a gate electrode and a semiconductor material underlying a gate dielectric. The scavenging material actively scavenges oxygen that diffuses toward the gate dielectric from above, or from the outside of, a dielectric gate spacer that can be formed around the oxygen-scavenging-material-including gate spacer.

Abstract translation: 包括清除材料和电介质材料的至少一层沉积在栅叠层上，随后进行各向异性蚀刻以形成含氧清除材料的栅间隔物。 含氧清除材料的栅极间隔物可以是包含清除纳米颗粒的栅极间隔物或含有扫气岛的栅极间隔物。 清除材料以防止栅极电极和栅极电介质下方的半导体材料之间的电短路的方式分布在含氧清除材料的栅极间隔物内。 清扫材料主动地清除从可以形成在含氧清除材料的栅极间隔物周围形成的介电栅极隔离物的上方或外部扩散到栅极电介质的氧。