公开(公告)号：US09552995B2

公开(公告)日：2017-01-24

申请号：US14555124

申请日：2014-11-26

Applicant: Intel Corporation

Inventor： Khang Choong Yong ,  Bok Eng Cheah ,  Teong Keat Beh ,  Howard L. Heck ,  Jackson Chung Peng Kong ,  Stephen H. Hall ,  Kooi Chi Ooi

IPC: H01L23/498 ,  H01L21/288 ,  H01L23/00 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/2885 ,  H01L21/76802 ,  H01L21/76879 ,  H01L23/48 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5383 ,  H01L24/13 ,  H01L2224/1302 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Some example forms relate to an electrical interconnect for an electronic package. The electrical interconnect includes a dielectric layer that includes a trench formed into one surface of the dielectric layer and a signal conductor that fills the trench and extends above the one surface of dielectric layer. The electrical interconnect further includes a conductive reference layer mounted on an opposing side of the dielectric layer. The conductive reference layer is electromagnetically coupled to the signal conductor when current passes through the signal conductor.

Abstract translation: 一些示例形式涉及电子封装的电互连。 电互连包括介电层，其包括形成在电介质层的一个表面中的沟槽和填充沟槽并在电介质层的一个表面上方延伸的信号导体。 电互连还包括安装在电介质层的相对侧上的导电参考层。 当电流通过信号导体时，导电参考层与信号导体电磁耦合。

公开(公告)号：USD773452S1

公开(公告)日：2016-12-06

申请号：US29539359

申请日：2015-09-14

Applicant: Intel Corporation

Designer： Bok Eng Cheah ,  Howe Yin Loo ,  Min Suet Lim ,  Jackson Chung Peng Kong ,  Poh Tat Oh

公开(公告)号：USD756349S1

公开(公告)日：2016-05-17

申请号：US29513077

申请日：2014-12-26

Applicant: Intel Corporation

Designer： Min Suet Lim ,  Bok Eng Cheah ,  Howe Yin Loo ,  Jackson Chung Peng Kong ,  Poh Tat Oh

公开(公告)号：US20160132077A1

公开(公告)日：2016-05-12

申请号：US14996568

申请日：2016-01-15

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Howe Yin Loo ,  Min Suet Lim ,  Jackon Chung Peng Kong ,  Poh Tat Oh

IPC: G06F1/16 ,  H05K5/02

CPC classification number: E05D3/06 ,  E05D11/0081 ,  G06F1/1615 ,  G06F1/1616 ,  G06F1/1618 ,  G06F1/1662 ,  G06F1/1677 ,  G06F1/1681 ,  G06F1/3218 ,  G06F1/3265 ,  H05K5/0226 ,  Y02D10/153 ,  Y10T16/522 ,  Y10T16/533 ,  Y10T16/5475

Abstract: Particular embodiments described herein provide for an electronic device, such as a notebook computer or laptop, which includes a circuit board coupled to a plurality of electronic components (which includes any type of components, elements, circuitry, etc.). One particular example implementation of the electronic device may include a low profile hinge design that includes a micro-hinge. The micro-hinge can couple a first element to a second element and can include a first attachment that couples to the first element, a second attachment that couples to the second element, and a plurality of linkages that couples the first attachment to the second attachment. The low profile hinge can further include a plurality of micro-hinges and a plurality of support rods.

公开(公告)号：US20160130849A1

公开(公告)日：2016-05-12

申请号：US14998225

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Howe Yin Loo ,  Min Suet Lim ,  Jackon Chung Peng Kong ,  Poh Tat Oh

IPC: E05D3/06 ,  E05D11/00 ,  G06F1/16

CPC classification number: E05D3/06 ,  E05D11/0081 ,  G06F1/1615 ,  G06F1/1616 ,  G06F1/1618 ,  G06F1/1662 ,  G06F1/1677 ,  G06F1/1681 ,  G06F1/3218 ,  G06F1/3265 ,  H05K5/0226 ,  Y02D10/153 ,  Y10T16/522 ,  Y10T16/533 ,  Y10T16/5475

Abstract: A personal computing device is provided with a first housing portion, a second housing portion, and a hinge joining the first housing portion to the second housing portion. The hinge is configured to allow the first housing portion to rotate substantially three-hundred-sixty degrees relative to the second housing portion. The hinge can be implemented as a plurality of interlinked parallel hinge segments, each hinge segment to rotate about a respective one of a plurality of parallel axes of the hinge to enable the rotation of the first housing portion.

Abstract translation: 个人计算设备设置有第一壳体部分，第二壳体部分和将第一壳体部分连接到第二壳体部分的铰链。 铰链被构造成允许第一壳体部分相对于第二壳体部分大致旋转三百六十度。 铰链可以实现为多个互连的平行铰链段，每个铰链段围绕铰链的多个平行轴线中的相应一个旋转，以使第一壳体部分能够旋转。

公开(公告)号：US12256487B2

公开(公告)日：2025-03-18

申请号：US17367674

申请日：2021-07-06

Applicant: Intel Corporation

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Jenny Shio Yin Ong ,  Seok Ling Lim ,  Chin Lee Kuan ,  Tin Poay Chuah

IPC: H05K1/02 ,  H05K3/46

Abstract: The present disclosure is directed to a hybrid dielectric interconnect stack for a printed circuit board having a first dielectric layer with a first dielectric constant and a first dielectric loss tangent positioned over an intermediate layer, which includes a first dielectric sublayer with a first sublayer dielectric constant and a first sublayer dielectric loss tangent, an embedded conductive layer, and a second dielectric sublayer with a second sublayer dielectric constant and a second sublayer dielectric loss tangent, in which the embedded conductive layer is positioned between the first and second dielectric sublayers, and a second dielectric layer with a second dielectric constant and a second dielectric loss tangent, in which the intermediate layer is positioned between the first and second dielectric layers.

公开(公告)号：US20240222346A1

公开(公告)日：2024-07-04

申请号：US18091228

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Seok Ling Lim ,  Jenny Shio Yin Ong ,  Kooi Chi Ooi ,  Jackson Chung Peng Kong

IPC: H01L25/18 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L21/56 ,  H01L23/3107 ,  H01L24/14 ,  H01L24/16 ,  H01L24/20 ,  H01L25/50 ,  H01L2224/1403 ,  H01L2224/16227 ,  H01L2224/211

Abstract: An apparatus is provided which comprises: a first package, a second package coupled with the first package, the second package comprising a mold layer having a recess on a first mold surface, a first plurality of devices adjacent to the recess and a metal redistribution layer (RDL) coupled to a second mold surface opposite the first mold surface, wherein the mold layer includes a first thickness, wherein the recess includes a second thickness, and wherein the second thickness is less than the first thickness, and an integrated circuit device coupled with both the second package at the recess and with the first package through a plurality of solder bumps. Other embodiments are also disclosed and claimed.

公开(公告)号：US11639623B2

公开(公告)日：2023-05-02

申请号：US16859452

申请日：2020-04-27

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Howe Yin Loo ,  Min Suet Lim ,  Jackson Chung Peng Kong ,  Poh Tat Oh

IPC: E05D3/06 ,  G06F1/16 ,  G06F1/3218 ,  G06F1/3234 ,  E05D11/00 ,  H05K5/02

Abstract: Particular embodiments described herein provide for an electronic device, such as a notebook computer or laptop, which includes a circuit board coupled to a plurality of electronic components (which includes any type of components, elements, circuitry, etc.). One particular example implementation of the electronic device may include a low profile hinge design that includes a micro-hinge. The micro-hinge can couple a first element to a second element and can include a first attachment that couples to the first element, a second attachment that couples to the second element, and a plurality of linkages that couples the first attachment to the second attachment. The low profile hinge can further include a plurality of micro-hinges and a plurality of support rods.

公开(公告)号：US20230124098A1

公开(公告)日：2023-04-20

申请号：US17503413

申请日：2021-10-18

Applicant: Intel Corporation

Inventor： Chin Lee Kuan ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

IPC: H01L23/00 ,  H01L23/552 ,  H01L23/498 ,  H01L21/48

Abstract: The present disclosure is directed to a semiconductor package including: a package substrate including a top surface, lateral sides and a bottom surface; a ball grid array including a plurality of solder balls coupled to the bottom surface; a stiffener including a bottom portion affixed to the bottom surface of the package substrate and a lateral portion extending from the bottom portion and affixed to the lateral sides of the package substrate, the bottom portion of the stiffener including a plurality of openings for the plurality of solder balls, wherein the top surface of the package substrate is substantially flush with a top surface of the lateral portion; and an electronic component coupled to the top surface of the package substrate.

公开(公告)号：US20230048835A1

公开(公告)日：2023-02-16

申请号：US17975223

申请日：2022-10-27

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Jenny Shio Yin Ong ,  Ping Ping Ooi ,  Seok Ling Lim

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: Disclosed embodiments include composite-bridge die-to-die interconnects that are on a die side of an integrated-circuit package substrate and that contacts two IC dice and a passive device that is in a molding material, where the molding material also contacts the two IC dice.