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    Method and system for digital pre-distortion using look-up table
    61.
    发明授权
    Method and system for digital pre-distortion using look-up table 有权

    公开(公告)号：US11658672B2

    公开(公告)日：2023-05-23

    申请号：US17455223

    申请日：2021-11-17

    Applicant: Intel Corporation

    Inventor： Ramon Sanchez ,  Kameran Azadet

    IPC: H03M1/10

    CPC classification number: H03M1/1052 ,  H03M1/1061

    Abstract: A digital predistortion system and method for pre-distorting an input to a non-linear system. The digital predistortion system includes a digital predistortion circuit and a memory. The digital predistortion circuit is configured to receive input data and modify the input data using at least one look-up table. The at least one look-up table is addressed by a signed real value of the input data. The memory is configured to store the at least one look-up table. The at least one look-up table is implemented based on a generalized memory polynomial model.

    Segmented digital-to-analog converter with subtractive dither
    62.
    发明授权
    Segmented digital-to-analog converter with subtractive dither 有权

    公开(公告)号：US11637560B2

    公开(公告)日：2023-04-25

    申请号：US17455221

    申请日：2021-11-17

    Applicant: Intel Corporation

    Inventor： Martin Clara ,  Daniel Gruber ,  Kameran Azadet

    IPC: H03M1/20 ,  H03M1/10

    Abstract: A segmented digital-to-analog converter (DAC) includes DAC segments, an overrange DAC, and a dither control circuit. Each DAC segment includes a plurality of DAC cells for generating an analog output signal based on input data to each DAC segment. The overrange DAC generates an analog output signal based on a control signal. The dither control circuit adds a dither to first input data supplied to a higher-order DAC segment, subtract a portion of the dither from second input data supplied to a lower-order DAC segment, and generate the control signal for subtracting a remaining portion of the dither from an output of the segmented DAC in an analog domain. The dither added to the first input data may be one of +1, 0, and −1 and the portion of the dither subtracted from the second input data may be a half of the dither added to the first input data.

    Apparatus for generating synchronized clock signals, elec-tronic system, base station and mobile device
    63.
    发明授权
    Apparatus for generating synchronized clock signals, elec-tronic system, base station and mobile device 有权

    公开(公告)号：US11378999B2

    公开(公告)日：2022-07-05

    申请号：US16724486

    申请日：2019-12-23

    Applicant: Intel Corporation

    Inventor： Yu-Shan Wang ,  Martin Clara ,  Daniel Gruber ,  Hundo Shin ,  Kameran Azadet

    IPC: G06F1/12 ,  G06F1/14 ,  G06F1/08

    Abstract: An apparatus for generating synchronized clock signals is provided. The apparatus comprises a first circuit comprising a clock divider circuit configured to receive a first clock signal and to generate a second clock signal by frequency dividing the first clock signal. Further, the apparatus comprises a one or more second circuits comprising a respective synchronization circuit configured to receive the first clock signal. The synchronization circuit of one of the one or more second circuits is configured to receive the second clock signal from the first circuit and to resample the second clock signal based on the first clock signal in order to generate a replica of the second clock signal that is in phase with the second clock signal.

    Digital-to-analog conversion system
    64.
    发明授权
    Digital-to-analog conversion system 有权

    公开(公告)号：US11239866B2

    公开(公告)日：2022-02-01

    申请号：US16924274

    申请日：2020-07-09

    Applicant: Intel Corporation

    Inventor： Daniel Gruber ,  Ramon Sanchez ,  Kameran Azadet ,  Martin Clara

    IPC: H04B1/00 ,  H04B1/04 ,  H03M1/66 ,  H04B1/10

    Abstract: A digital-to-analog conversion system is provided. The digital-to-analog conversion system includes a digital-to-analog converter configured to receive a pre-distorted digital signal from a digital circuit, and to generate an analog signal based on the pre-distorted digital signal. Further, the digital-to-analog conversion system includes a feedback loop for providing a digital feedback signal to the digital circuit. The feedback loop includes an analog-to-digital converter configured to generate the digital feedback signal based on the analog signal, and wherein a sample rate of the analog-to-digital converter is lower than a sample rate of the digital-to-analog converter.

    Analog-to-digital converter system, transceiver, base station and mobile device
    65.
    发明授权
    Analog-to-digital converter system, transceiver, base station and mobile device 有权

    公开(公告)号：US11044137B1

    公开(公告)日：2021-06-22

    申请号：US16724458

    申请日：2019-12-23

    Applicant: Intel Corporation

    Inventor： Kameran Azadet ,  Martin Clara ,  Daniel Gruber ,  Christian Lindholm ,  Hundo Shin

    IPC: H03M1/36 ,  H04L27/36 ,  H03M1/06 ,  H03M1/10 ,  H04B1/04

    Abstract: An Analog-to-Digital Converter, ADC, system is provided. The ADC system comprises a plurality of ADC circuits and a first input for receiving a transmit signal of a transceiver. One ADC circuit of the plurality of ADC circuits is coupled to the first input and configured to provide first digital data based on the transmit signal. The ADC system further comprises a second input for receiving a receive signal of the transceiver. The other ADC circuits of the plurality of ADC circuits are coupled to the second input, wherein the other ADC circuits of the plurality of ADC circuits are time-interleaved and configured to provide second digital data based on the receive signal. Additionally, the ADC system comprises a first output configured to output digital feedback data based on the first digital data, and a second output configured to output digital receive data based on the second digital data.

    CHANNEL ESTIMATION USING PEAK CANCELLATION
    66.
    发明申请
    CHANNEL ESTIMATION USING PEAK CANCELLATION 审中-公开

    公开(公告)号：US20180287827A1

    公开(公告)日：2018-10-04

    申请号：US15475783

    申请日：2017-03-31

    Applicant: Intel Corporation

    Inventor： Albert Molina ,  Kameran Azadet

    IPC: H04L25/02 ,  H04L27/26

    CPC classification number: H04L25/0228 ,  H04B7/0413 ,  H04J13/0062 ,  H04L27/2647

    Abstract: An apparatus and a method for estimation a wireless channel are disclosed. For example, the method correlates, by a correlator, a plurality of signals of a combined signal received by a receive antenna over the wireless channel from a plurality of transmit antennas, with respective DMRSs of the plurality of transmit antennas, converts, by a converter, the correlated plurality of signals from frequency to time domain, iteratively peak cancels, by a peak canceller, a largest peak of the combined impulse response and stores a scaling factor and location pair of the cancelled peak until a magnitude of a next largest peak is below a predetermined threshold, assigns, by an assigner, each of the scaling factor and location pairs to a transmit antenna, and estimates, by an estimator, for each of the plurality of transmit antennas, the wireless channel based on the assigned scaling factor and location pairs.

    Arbitrary noise shaping transmitter with receive band notches
    67.
    发明授权
    Arbitrary noise shaping transmitter with receive band notches 有权

    公开(公告)号：US10044367B1

    公开(公告)日：2018-08-07

    申请号：US15671888

    申请日：2017-08-08

    Applicant: Intel Corporation

    Inventor： Kameran Azadet ,  Ramon Sanchez

    IPC: H03M3/00 ,  H03L7/20 ,  H03L7/16 ,  G10L19/03 ,  H03M1/00

    Abstract: Techniques for generating signals with arbitrary noise shaping are discussed. One example apparatus configured to be employed within a transmitter can comprise a noise shaper configured to: receive an input signal xq; and apply noise shaping to the input signal xq to generate a noise shaped output signal yq, wherein an in-band noise of the noise shaped output signal yq is below an in-band noise threshold of a spectral mask associated with the noise shaper, wherein an out-of-band noise of the noise shaped output signal yq is below an out-of-band noise threshold of the spectral mask, and wherein a noise of the output signal yq in each of a plurality of bandpass regions is below an associated noise threshold for that bandpass region of the spectral mask.

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