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    Method for manufacturing a bipolar junction transistor
    61.
    发明授权
    Method for manufacturing a bipolar junction transistor 有权
    双极结型晶体管的制造方法

    公开(公告)号：US06734073B2

    公开(公告)日：2004-05-11

    申请号：US10007931

    申请日：2001-12-07

    申请人： Gregory E. Howard ,  Angelo Pinto

    发明人： Gregory E. Howard ,  Angelo Pinto

    IPC分类号： H01L21331

    CPC分类号： H01L29/66272 ,  H01L21/8249 ,  H01L29/0804 ,  H01L29/7322

    摘要： According to one embodiment of the invention, a method for manufacturing a bipolar junction transistor includes implanting a first base dopant in a semiconductor substrate, forming an epitaxial layer outwardly from the semiconductor substrate, and forming a dielectric layer outwardly from the epitaxial layer. The method also includes etching a first portion of the dielectric layer to form an emitter region, forming an emitter polysilicon layer on the semiconductor substrate, and implanting an emitter dopant in the emitter polysilicon layer. The method further includes etching a portion of the emitter polysilicon layer and a second portion of the dielectric layer to form an emitter polysilicon region having sidewalls, forming nitride regions on the sidewalls, and implanting a second base dopant in the semiconductor substrate. After implanting the second base dopant, an annealing process is performed for the semiconductor substrate to form an emitter and a base.

    摘要翻译： 根据本发明的一个实施例，制造双极结型晶体管的方法包括：在半导体衬底中注入第一基极掺杂剂，从半导体衬底向外形成外延层，以及从外延层向外形成介电层。 该方法还包括蚀刻电介质层的第一部分以形成发射极区域，在半导体衬底上形成发射极多晶硅层，以及在发射极多晶硅层中注入射极掺杂剂。 该方法还包括蚀刻发射极多晶硅层的一部分和电介质层的第二部分以形成具有侧壁的发射极多晶硅区域，在侧壁上形成氮化物区域，并在半导体衬底中注入第二基极掺杂剂。 在注入第二基质掺杂剂之后，对半导体衬底进行退火处理以形成发射极和基极。

    PNP lateral bipolar electronic device and corresponding manufacturing process
    63.
    发明授权
    PNP lateral bipolar electronic device and corresponding manufacturing process 有权
    PNP横向双极电子器件及相应的制造工艺

    公开(公告)号：US06657279B1

    公开(公告)日：2003-12-02

    申请号：US09637956

    申请日：2000-08-11

    申请人： Angelo Pinto ,  Carlo Alemanni

    发明人： Angelo Pinto ,  Carlo Alemanni

    IPC分类号： H01L29735

    CPC分类号： H01L29/6625 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/735

    摘要： The invention relates to a process for making a lateral PNP bipolar electronic device integrated monolithically on a semiconductor substrate together with other bipolar devices of the NPN type, said device being incorporated to an electrically insulated multilayer structure. The device includes a semiconductor substrate doped with impurities of the P type; a first buried layer doped with impurities of the N type to form a base region; and a second layer, overlying the first and having conductivity of the N type, to form an active area with opposite collector and emitter regions being formed in said active area and separated by a base channel region. The width of the base channel region is defined essentially by a contact opening formed above an oxide layer deposited over the base channel region. Advantageously, the contact opening is formed by shifting an emitter mask.

    摘要翻译： 本发明涉及一种用于制造横向PNP双极电子器件的方法，其与NPN型的其它双极器件一体地集成在半导体衬底上，所述器件被并入到电绝缘的多层结构中。 该器件包括掺杂有P型杂质的半导体衬底; 掺杂有N型杂质的第一掩埋层以形成基极区; 以及覆盖第一层并具有N型导电性的第二层，以形成有源区域，其中相反的集电极和发射极区域形成在所述有源区域中并由基极沟道区域分隔开。 基本通道区域的宽度基本上由形成在沉积在基底通道区域上的氧化物层上方的接触开口限定。 有利地，通过移动发射器掩模来形成接触开口。

    Manufacturing process of a germanium implanted HBT bipolar transistor
    64.
    发明授权
    Manufacturing process of a germanium implanted HBT bipolar transistor 有权
    锗注入HBT双极晶体管的制造工艺

    公开(公告)号：US06624017B1

    公开(公告)日：2003-09-23

    申请号：US09724563

    申请日：2000-11-27

    申请人： Salvatore Lombardo ,  Maria Concetta Nicotra ,  Angelo Pinto

    发明人： Salvatore Lombardo ,  Maria Concetta Nicotra ,  Angelo Pinto

    IPC分类号： H01L218249

    CPC分类号： H01L29/66242 ,  H01L21/26506

    摘要： A process fabricates a vertical structure high carrier mobility transistor on a substrate of crystalline silicon doped with impurities of the N type, the transistor having a collector region located at a lower portion of the substrate. The process includes: defining a window in the semiconductor substrate; providing a first implantation of germanium atoms through said window; providing a second implantation of acceptor dopants through said window to define a base region; applying an RTA treatment, or treatment in an oven, to re-construct the crystal lattice within the semiconductor substrate comprising a silicon/germanium alloy; forming a first thin dielectric layer of silicon dioxide by chemical vapor deposition; depositing a second dielectric layer onto said first dielectric layer; depositing a polysilicon layer onto said second dielectric layer; etching away, within the window region, said first and second dielectric layers, and the polysilicon layer, to expose the base region and form isolation spacers at the window edges; and forming an N-doped emitter in the base and window regions. This fabrication process is specially attentive to the formation of the silicon dioxide SiO2/GexSi1−x interface present in vertical structure HBT transistors, if isolation spacers are to be formed. The fabrication process allows the frequency field of application of HBT transistors to be further extended, while eliminating deviations of the base currents from the ideal.

    摘要翻译： 一种工艺在掺杂有N型杂质的晶体硅的衬底上制造垂直结构的高载流子迁移率晶体管，晶体管具有位于衬底下部的集电极区域。 该方法包括：在半导体衬底中限定窗口; 提供通过所述窗口的锗原子的第一次注入; 提供通过所述窗口的受体掺杂剂的第二次注入以限定基极区域; 在烘箱中进行RTA处理或处理，以重新构建包括硅/锗合金的半导体衬底内的晶格; 通过化学气相沉积形成二氧化硅的第一薄介电层; 将第二介电层沉积到所述第一介电层上; 在所述第二电介质层上沉积多晶硅层; 在窗口区域内蚀刻所述第一和第二介电层以及多晶硅层，以露出基部区域并在窗口边缘处形成隔离间隔物; 以及在基极和窗口区域中形成N掺杂的发射极。 如果要形成隔离间隔物，则该制造工艺特别注意垂直结构HBT晶体管中存在的二氧化硅SiO 2 / G x Si 1-x界面的形成。 制造工艺允许HBT晶体管的应用频率场进一步延长，同时消除基极电流与理想电流的偏差。

    Method of manufacturing a vertical-channel MOSFET
    65.
    发明授权
    Method of manufacturing a vertical-channel MOSFET 有权
    制造垂直沟道MOSFET的方法

    公开(公告)号：US06362025B1

    公开(公告)日：2002-03-26

    申请号：US09441575

    申请日：1999-11-17

    申请人： Davide Patti ,  Angelo Pinto

    发明人： Davide Patti ,  Angelo Pinto

    IPC分类号： H01L21332

    CPC分类号： H01L29/66666 ,  H01L21/76221 ,  H01L21/763 ,  H01L21/8249 ,  H01L29/7827

    摘要： A submicrometer vertical-channel MOSFET of high quality and reproducibility is produced by a method compatible with DPSA technology. The method steps are performed on a wafer of semiconductor material having a layer with n conductivity. First, n impurity ions and p impurity ions are implanted in an area of the layer and the wafer is subjected to a high-temperature treatment. The impurities, the implantation doses and energies, and the high-temperature treatment time and temperature being such as to form a first p region, and a second n region which forms a pn junction with the first region. A trench is hollowed out which intersects the first region and the second regions. The method further includes forming a dielectric coating on the lateral surface of the trench, depositing electrically-conductive material in the trench in contact with the dielectric, and forming elements for electrical contact with the n conductivity layer, with the second region, and with the electrically-conductive material inside the trench, to produce drain, source and gate electrodes of the MOSFET, respectively.

    摘要翻译： 通过与DPSA技术相兼容的方法生产高质量和重复性的亚微米垂直沟道MOSFET。 方法步骤在具有n导电性层的半导体材料的晶片上进行。 首先，将n种杂质离子和p杂质离子注入到该层的区域中，并对晶片进行高温处理。 杂质，注入剂量和能量以及高温处理时间和温度等于形成第一p区，以及与第一区形成pn结的第二n区。 挖沟的沟槽与第一区域和第二区域相交。 该方法还包括在沟槽的侧表面上形成电介质涂层，在与电介质接触的沟槽中沉积导电材料，以及形成用于与第n个导电层与第二区域电接触的元件，以及与 沟槽内的导电材料，分别产生MOSFET的漏极，源极和栅极。

    INTEGRATION SCHEME FOR CHANGING CRYSTAL ORIENTATION IN HYBRID ORIENTATION TECHNOLOGY (HOT) USING DIRECT SILICON BONDED (DSB) SUBSTRATES
    69.
    发明申请
    INTEGRATION SCHEME FOR CHANGING CRYSTAL ORIENTATION IN HYBRID ORIENTATION TECHNOLOGY (HOT) USING DIRECT SILICON BONDED (DSB) SUBSTRATES 有权
    使用直接硅结合（DSB）基板在混合方向技术（热）中改变晶体取向的集成方案

    公开(公告)号：US20110108893A1

    公开(公告)日：2011-05-12

    申请号：US13007098

    申请日：2011-01-14

    申请人： Angelo Pinto ,  Frank S. Johnson ,  Benjamin P. McKee ,  Shaofeng Yu

    发明人： Angelo Pinto ,  Frank S. Johnson ,  Benjamin P. McKee ,  Shaofeng Yu

    IPC分类号： H01L27/092

    CPC分类号： H01L27/0928 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/76224 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/7833

    摘要： Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Methods such as amorphization and templated recrystallization (ATR) have disadvantages for fabrication of deep submicron CMOS. This invention is a method of forming an integrated circuit (IC) which has (100) and (110)-oriented regions. The method forms a directly bonded silicon (DSB) layer of (110)-oriented silicon on a (100)-oriented substrate. The DSB layer is removed in the NMOS regions and a (100)-oriented silicon layer is formed by selective epitaxial growth (SEG), using the substrate as the seed layer. NMOS transistors are formed on the SEG layer, while PMOS transistors are formed on the DSB layer. An integrated circuit formed with the inventive method is also disclosed.

    摘要翻译： 在CMOS IC中的MOS晶体管中优化载流子迁移率需要为PMOS形成用于NMOS和（110）区域的（100）取向的硅区域。 诸如非晶化和模板重结晶（ATR）的方法具有制造深亚微米CMOS的缺点。 本发明是形成具有（100）和（110）取向区域的​​集成电路（IC）的方法。 该方法在（100）取向的衬底上形成（110）取向的硅的直接键合的硅（DSB）层。 在NMOS区域中去除DSB层，并且使用基底作为种子层，通过选择性外延生长（SEG）形成（100）取向硅层。 在SEG层上形成NMOS晶体管，而在DSB层上形成PMOS晶体管。 还公开了用本发明方法形成的集成电路。