公开(公告)号：US20110197086A1

公开(公告)日：2011-08-11

申请号：US13119958

申请日：2008-09-18

申请人： Jochen Rivoir

发明人： Jochen Rivoir

IPC分类号： G06F1/04

CPC分类号： G01R31/31725 ,  G01R31/31726 ,  G01R31/3193 ,  G01R31/31937 ,  H04L25/0262 ,  H04L43/50 ,  H04L63/0428

摘要： A data processing unit has a time information provider for processing a clock or a strobe signal, configured to provide a digitized clock or strobe time information on the basis of the clock or strobe signal and at least one data extraction unit, coupled to the time information provider and configured to select data from a sequence of data samples of a data signal depending on the digitized clock or strobe time information.

摘要翻译： 数据处理单元具有用于处理时钟或选通信号的时间信息提供器，其被配置为基于时钟或选通信号提供数字化时钟或选通时间信息，以及耦合到时间信息的至少一个数据提取单元 提供商并且被配置为根据数字化时钟或选通时间信息从数据信号的数据样本序列中选择数据。

公开(公告)号：US07672804B2

公开(公告)日：2010-03-02

申请号：US11897847

申请日：2007-08-31

申请人： Jochen Rivoir

发明人： Jochen Rivoir

IPC分类号： G01R31/00 ,  G06F19/00

CPC分类号： G01R31/316 ,  G01R19/0038 ,  G01R19/25 ,  G01R23/20 ,  G01R31/2839 ,  G01R31/31708

摘要： A method and a corresponding system for testing an analog signal under test includes using knowledge of at least one parameter of the signal under test. The method includes generating a reference signal using the knowledge of at least one parameter of the signal under test, combining the generated reference signal with the signal under test, resulting in a combination signal, and evaluating the combination signal for testing the signal under test.

摘要翻译： 用于测试被测信号的方法和相应的系统包括使用被测信号的至少一个参数的知识。 所述方法包括使用所测试的信号的至少一个参数的知识来生成参考信号，将所生成的参考信号与被测信号组合，得到组合信号，并评估组合信号以测试被测信号。

公开(公告)号：US07414558B2

公开(公告)日：2008-08-19

申请号：US11489431

申请日：2006-07-19

申请人： Jochen Rivoir ,  Holger Engelhard

发明人： Jochen Rivoir ,  Holger Engelhard

IPC分类号： H03M1/66

CPC分类号： H03M1/74

摘要： A method for converting a digital signal to an analog signal, said method including a plurality of signal sources, preferably current sources, one or more of said signal sources being variable output signal magnitude sources, said method including the steps of setting the output signal magnitudes of the one or more variable output signal magnitude sources by individual setting signals being input signals for said respective variable output signal magnitude sources, wherein said conversion is adaptable on a per signal basis in response to needs concerning bandwidth and/or accuracy for achieving a trade-off between sample-rate and resolution of said conversion.

摘要翻译： 一种用于将数字信号转换为模拟信号的方法，所述方法包括多个信号源，优选地是电流源，所述信号源中的一个或多个是可变输出信号幅度源，所述方法包括以下步骤：设置输出信号幅度 一个或多个可变输出信号幅度源的单个设置信号是用于所述各个可变输出信号幅度源的输入信号，其中响应于关于实现交易的带宽和/或准确性的需求，所述转换适应每个信号基础 取样率和分辨率之间的转换。

公开(公告)号：US07366937B2

公开(公告)日：2008-04-29

申请号：US11158645

申请日：2005-06-22

申请人： Jochen Rivoir

发明人： Jochen Rivoir

IPC分类号： H03B19/00

CPC分类号： H03L7/18 ,  G06F1/12 ,  H03L7/1976

摘要： The present invention relates to a method for synchronizing a number of digital clocks to a synchronizing signal, said method comprising generating centrally a reference clock, synthesizing said digital clocks from said reference clock using a clock multiplier, respectively, resetting said clock multiplier in response to said synchronizing signal, and masking an output signal of said clock multiplier during settling time of said clock multiplier.

摘要翻译： 本发明涉及一种用于将多个数字时钟同步到同步信号的方法，所述方法包括以集中方式产生参考时钟，使用时钟乘法器分别从所述参考时钟合成所述数字时钟，以响应于 所述同步信号，并且在所述时钟乘法器的稳定时间期间屏蔽所述时钟乘法器的输出信号。

公开(公告)号：US20070266288A1

公开(公告)日：2007-11-15

申请号：US11435064

申请日：2006-05-15

申请人： Erik Volkerink ,  Hugh Wallace ,  Klaus-Dieter Hilliges ,  Ajay Khoche ,  Jochen Rivoir

发明人： Erik Volkerink ,  Hugh Wallace ,  Klaus-Dieter Hilliges ,  Ajay Khoche ,  Jochen Rivoir

IPC分类号： G01R31/28

CPC分类号： G01R31/31907

摘要： An adaptive test system includes one or more reconfigurable test boards, with each test board including at least one re-configurable test processor. The re-configurable test processors can transmit communicate with one another using an inter-processor communications controller associated with each re-configurable test processor. The communications include configuration information, control information, communication protocols, stimulus data, and responses. Configuration information and stimulus data can also be read from a memory. Configuration information is used to configure one or more re-configurable test processors. Once configured, the re-configurable test processor or processors process the data in order to generate one or more test signals. The one or more test signals are then used to test a DUT.

摘要翻译： 自适应测试系统包括一个或多个可重新配置的测试板，每个测试板包括至少一个可重新配置的测试处理器。 可重新配置的测试处理器可以使用与每个可重新配置的测试处理器相关联的处理器间通信控制器彼此进行通信。 通信包括配置信息，控制信息，通信协议，刺激数据和响应。 还可以从存储器读取配置信息和激励数据。 配置信息用于配置一个或多个可重新配置的测试处理器。 一旦配置，可重新配置的测试处理器或处理器处理数据，以产生一个或多个测试信号。 然后使用一个或多个测试信号来测试DUT。

公开(公告)号：US20070024482A1

公开(公告)日：2007-02-01

申请号：US11489431

申请日：2006-07-19

申请人： Jochen Rivoir ,  Holger Engelhard

发明人： Jochen Rivoir ,  Holger Engelhard

IPC分类号： H03M1/66

CPC分类号： H03M1/74

摘要： A method for converting a digital signal to an analog signal, said method including a plurality of signal sources, preferably current sources, one or more of said signal sources being variable output signal magnitude sources, said method including the steps of setting the output signal magnitudes of the one or more variable output signal magnitude sources by individual setting signals being input signals for said respective variable output signal magnitude sources, wherein said conversion is adaptable on a per signal basis in response to needs concerning bandwidth and/or accuracy for achieving a trade-off between sample-rate and resolution of said conversion.

摘要翻译： 一种用于将数字信号转换为模拟信号的方法，所述方法包括多个信号源，优选地是电流源，所述信号源中的一个或多个是可变输出信号幅度源，所述方法包括以下步骤：设置输出信号幅度 一个或多个可变输出信号幅度源的单个设置信号是用于所述各个可变输出信号幅度源的输入信号，其中响应于关于实现交易的带宽和/或准确性的需求，所述转换适应每个信号基础 取样率和分辨率之间的转换。

公开(公告)号：US07136770B2

公开(公告)日：2006-11-14

申请号：US10700831

申请日：2003-11-03

申请人： Jochen Rivoir ,  John McLaughlin ,  Joseph M. Gorin ,  Moray Denham Rumney ,  Matthew Johnson ,  Robert Locascio ,  Peter J. Cain ,  David H. Molinari ,  George S. Moore

发明人： Jochen Rivoir ,  John McLaughlin ,  Joseph M. Gorin ,  Moray Denham Rumney ,  Matthew Johnson ,  Robert Locascio ,  Peter J. Cain ,  David H. Molinari ,  George S. Moore

IPC分类号： G01R31/00 ,  G01R31/14

CPC分类号： G06F11/3447

摘要： Using component-level test data to reduce system test. By modeling a system, sensitivity analysis reveals critical components and parameters of those components required to meet system performance parameters. Critical components are tested for these parameters, and these measurements associated with the components. Systems may be assembled which are modeled to meet the system performance parameters based on the model and the measured parameters. Systems may be assembled and calibration coefficients derived and applied from the model and the measured parameters.

摘要翻译： 使用组件级测试数据来减少系统测试。 通过对系统建模，灵敏度分析揭示了满足系统性能参数所需的关键组件和参数。 对这些参数测试关键部件，这些测量与组件相关。 可以组装系统，其被建模以基于模型和测量的参数来满足系统性能参数。 可以组装系统并从模型和测量参数导出和应用校准系数。

公开(公告)号：US06993695B2

公开(公告)日：2006-01-31

申请号：US09875567

申请日：2001-06-06

申请人： Jochen Rivoir

发明人： Jochen Rivoir

IPC分类号： G01R31/28 ,  G06K5/04

CPC分类号： H04L1/242 ,  H04L25/493

摘要： A method and apparatus for testing a device using transition timestamp are used to evaluate output signals from the device. The method comprises the steps of performing timing tests on a signal from the device; and independently carrying out bit-level tests on a signal from the device. The independent timing tests and bit-level tests can be performed in parallel. The bit-level tests and apparatus comprise iteratively measuring a coarse timestamp for a transition in the signal and comparing the measured coarse timestamp to an expected timestamp to determine whether the device meets specifications. Whether the device meets specifications depends on whether, during the comparison step, the presence of a bit-level fault is detected. The apparatus and method may comprise Skew Fault detection, Bit Fault detection, No Coverage Warning detection and/or Drift Fault detection. An automatic testing system for testing devices comprises subsystems that incorporate the apparatus and method.

公开(公告)号：US20050289427A1

公开(公告)日：2005-12-29

申请号：US11158499

申请日：2005-06-22

申请人： Jochen Rivoir

发明人： Jochen Rivoir

IPC分类号： G01R31/317 ,  G01R31/319 ,  G06F1/08 ,  H03L7/197 ,  G01R31/28 ,  G06F11/00

CPC分类号： G01R31/31709 ,  G01R31/319 ,  G01R31/31922 ,  H03L7/1974 ,  H03L7/1976

摘要： A method and system for synthesizing digital clock signals for an electronic device under test having a plurality of pins, said method including generating centrally a reference clock, and distributing said reference clock to a number of electronic circuits, each of said electronic circuit having a test signal processor controlling electrically said pins of said device under test with predetermined signal pattern, characterized by synthesizing locally at said test signal processor a digital clock signal, said digital clock signal being individual for said pin of said device under test electrically controlled by said test signal processor.

摘要翻译： 一种用于对被测电子设备合成数字时钟信号的方法和系统，具有多个引脚，所述方法包括在中央产生参考时钟，并将所述参考时钟分配给多个电子电路，每个所述电子电路具有测试 信号处理器用预定的信号模式对被测试的所述设备的所述引脚进行电气控制，其特征在于在所述测试信号处理器处局部地合成数字时钟信号，所述数字时钟信号对于所测试的被测器件的引脚是个别的，由所述测试信号电控制 处理器。

公开(公告)号：US20050289405A1

公开(公告)日：2005-12-29

申请号：US11158645

申请日：2005-06-22

申请人： Jochen Rivoir

发明人： Jochen Rivoir

IPC分类号： G01R31/28 ,  G06F1/04 ,  G06F1/12 ,  G06K5/04 ,  G11B5/00 ,  G11B20/20 ,  H03L7/06 ,  H03L7/18 ,  H03L7/197 ,  H04L7/04

CPC分类号： H03L7/18 ,  G06F1/12 ,  H03L7/1976

摘要： The present invention relates to a method for synchronizing a number of digital clocks to a synchronizing signal, said method comprising generating centrally a reference clock, synthesizing said digital clocks from said reference clock using a clock multiplier, respectively, resetting said clock multiplier in response to said synchronizing signal, and masking an output signal of said clock multiplier during settling time of said clock multiplier.

摘要翻译： 本发明涉及一种用于将多个数字时钟同步到同步信号的方法，所述方法包括以集中方式产生参考时钟，使用时钟乘法器分别从所述参考时钟合成所述数字时钟，以响应于 所述同步信号，并且在所述时钟乘法器的稳定时间期间屏蔽所述时钟乘法器的输出信号。