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112 条记录 (耗时 0.031 秒)

    Complementary metal-oxide-semiconductor translator
    61.
    发明授权
    Complementary metal-oxide-semiconductor translator 失效
    互补金属氧化物半导体转换器

    公开(公告)号：US4958132A

    公开(公告)日：1990-09-18

    申请号：US349116

    申请日：1989-05-09

    申请人： William C. Plants

    发明人： William C. Plants

    IPC分类号： H03F1/34 ,  H03K19/0185

    CPC分类号： H03F1/342 ,  H03K19/018521

    摘要： A CMOS translator which includes an amplifier having an input node and an output node; a first clamp for providing a clamped feedback signal from the output node to the input node of the amplifier; and a second clamp for providing a clamped feedforward signal from the input node to the output of the amplifier. ECL signals are translated up to CMOS voltage levels with high speed, low power consumption via a circuit with requires minimal die area. The unique clamping arrangement provides a self-biasing feature which affords a large error margin.

    Common doped region with separate gate control for a logic compatible non-volatile memory cell
    62.
    发明授权
    Common doped region with separate gate control for a logic compatible non-volatile memory cell 有权
    具有用于逻辑兼容的非易失性存储单元的单独栅极控制的公共掺杂区域

    公开(公告)号：US08873302B2

    公开(公告)日：2014-10-28

    申请号：US13284795

    申请日：2011-10-28

    申请人： David Edward Fisch ,  William C. Plants ,  Michael Curtis Parris

    发明人： David Edward Fisch ,  William C. Plants ,  Michael Curtis Parris

    IPC分类号： G11C11/34 ,  G11C16/00 ,  G11C16/04 ,  H01L29/423 ,  H01L27/115 ,  H01L29/788

    CPC分类号： H01L29/42324 ,  G11C16/00 ,  G11C16/0416 ,  H01L27/11558 ,  H01L29/7881

    摘要： An array of memory cells, in which one or more memory cells have a common doped region. Each memory cell includes a transistor with a floating gate, source and drain regions, and separate gate and drain voltage controls. Each memory cell also includes a coupling capacitor electrically coupled to and located laterally from the floating gate. In the array, first bit lines are oriented in a first direction, wherein a first bit line is coupled to drain regions of transistors that are arranged in a column. The array includes second bit lines also oriented in the first direction, wherein a second bit line is coupled to source regions of transistors that are arranged in a column. The array also includes word lines oriented in a second direction, wherein each word line is coupled to control gates of coupling capacitors that are arranged in a row.

    摘要翻译： 存储单元阵列，其中一个或多个存储单元具有公共掺杂区域。 每个存储单元包括具有浮置栅极，源极和漏极区域以及单独的栅极和漏极电压控制的晶体管。 每个存储器单元还包括电耦合到浮动栅极并且横向浮置的栅极的耦合电容器。 在阵列中，第一位线在第一方向上定向，其中第一位线耦合到排列在列中的晶体管的漏极区域。 该阵列包括也在第一方向上定向的第二位线，其中第二位线耦合到排列在列中的晶体管的源极区域。 阵列还包括在第二方向上定向的字线，其中每个字线耦合到排列成一行的耦合电容器的控制栅极。

    Field programmable gate array and microcontroller system-on-a-chip
    63.
    发明授权
    Field programmable gate array and microcontroller system-on-a-chip 有权
    现场可编程门阵列和微控制器片上系统

    公开(公告)号：US07886130B2

    公开(公告)日：2011-02-08

    申请号：US12345409

    申请日：2008-12-29

    申请人： Arunangshu Kundu ,  Arnold Goldfein ,  William C. Plants ,  David Hightower

    发明人： Arunangshu Kundu ,  Arnold Goldfein ,  William C. Plants ,  David Hightower

    IPC分类号： G06F15/00 ,  G06F15/76

    CPC分类号： G06F15/7842 ,  G06F15/7867

    摘要： A system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the field programmable gate array core, a microcontroller, a microcontroller virtual component interface translator having input and outputs, wherein the inputs are connected to the microcontroller, a system bus connected to the outputs of the field programmable gate array virtual component interface translator and also to the outputs of said microcontroller virtual component interface translator, and direct connections between the microcontroller and the routing resources of the field programmable gate array core.

    摘要翻译： 片上系统集成电路具有具有逻辑集群，静态随机存取存储器模块和路由资源的现场可编程门阵列核心，具有输入和输出的现场可编程门阵列虚拟组件接口转换器，其中输入被连接 到现场可编程门阵列核心，微控制器，具有输入和输出的微控制器虚拟组件接口转换器，其中输入连接到微控制器，连接到现场可编程门阵列虚拟组件接口转换器的输出的系统总线，以及 到所述微控制器虚拟组件接口转换器的输出，以及微控制器与现场可编程门阵列核心的路由资源之间的直接连接。

    Deglitching circuits for a radiation-hardened static random access memory based programmable architecture
    64.
    发明授权
    Deglitching circuits for a radiation-hardened static random access memory based programmable architecture 失效
    用于基于辐射硬化的静态随机存取存储器可编程架构的脱斜电路

    公开(公告)号：US07672153B2

    公开(公告)日：2010-03-02

    申请号：US12172860

    申请日：2008-07-14

    申请人： William C. Plants

    发明人： William C. Plants

    IPC分类号： G11C11/00

    CPC分类号： G11C11/4125

    摘要： A method for providing a deglitching circuit for a radiation tolerant static random access memory (SRAM) comprising: providing a configuration memory having a plurality of configuration bits; coupling read and write circuitry to the configuration memory for configuring the plurality of configuration bits; coupling a radiation hard latch to a programmable element, the radiation hard latch controlling the programmable element; and providing an interface that couples at least one of the plurality of configuration bits to the radiation hard latch when the write circuitry writes to the at least one of the plurality of configuration bits.

    摘要翻译： 一种用于为耐辐射静态随机存取存储器（SRAM）提供消旋电路的方法，包括：提供具有多个配置位的配置存储器; 将读和写电路耦合到配置存储器，用于配置多个配置位; 将辐射硬锁存器耦合到可编程元件，所述辐射硬锁存器控制所述可编程元件; 以及当所述写电路写入所述多个配置位中的至少一个配置位时，提供将所述多个配置位中的至少一个耦合到所述辐射硬锁存器的接口。

    Delay locked loop for an FPGA architecture
    66.
    发明授权
    Delay locked loop for an FPGA architecture 有权
    延迟锁定环路用于FPGA架构

    公开(公告)号：US07484113B1

    公开(公告)日：2009-01-27

    申请号：US11561695

    申请日：2006-11-20

    申请人： William C. Plants ,  Nikhil Mazumder ,  Arunangshu Kundu ,  James Joseph ,  Wayne W. Wong

    发明人： William C. Plants ,  Nikhil Mazumder ,  Arunangshu Kundu ,  James Joseph ,  Wayne W. Wong

    IPC分类号： G06F1/08

    CPC分类号： G06F1/10

    摘要： A DLL provides a deskew mode for aligning a reference clock that passes through a clock distribution tree to a feedback by adding additional delay to the feedback clock to align the feedback clock with reference clock at one cycle later. A 0 ns clock-to-out mode is provided by adding additional delay to account for an input buffer into a feedback path. The feedback clock can be doubled by a clock doubler with 50% duty cycle adjustment disposed in the feedback path. Flexible timing is aligning the reference clock to the feedback clock is obtained with additional delay elements disposed in the feedback and reference clock paths.

    摘要翻译： DLL提供了一种去偏移模式，用于将通过时钟分配树的参考时钟对准到反馈，通过向反馈时钟添加额外的延迟，将反馈时钟与参考时钟对齐在一个周期之后。 通过添加额外的延迟来将输入缓冲区考虑到反馈路径中，提供0 ns时钟到输出模式。 反馈时钟可以通过在反馈路径中布置的50％占空比调整的时钟倍增器加倍。 灵活的定时是将参考时钟对齐到反馈时钟，其通过设置在反馈和参考时钟路径中的附加延迟元件获得。

    DEGLITCHING CIRCUITS FOR A RADIATION-HARDENED STATIC RANDOM ACCESS MEMORY BASED PROGRAMMABLE ARCHITECTURE
    67.
    发明申请
    DEGLITCHING CIRCUITS FOR A RADIATION-HARDENED STATIC RANDOM ACCESS MEMORY BASED PROGRAMMABLE ARCHITECTURE 失效
    基于辐射硬化静态随机访问存储器的可编程架构的分级电路

    公开(公告)号：US20080298116A1

    公开(公告)日：2008-12-04

    申请号：US12172860

    申请日：2008-07-14

    申请人： William C. Plants

    发明人： William C. Plants

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G11C11/4125

    摘要： A method for providing a deglitching circuit for a radiation tolerant static random access memory (SRAM) comprising: providing a configuration memory having a plurality of configuration bits; coupling read and write circuitry to the configuration memory for configuring the plurality of configuration bits; coupling a radiation hard latch to a programmable element, the radiation hard latch controlling the programmable element; and providing an interface that couples at least one of the plurality of configuration bits to the radiation hard latch when the write circuitry writes to the at least one of the plurality of configuration bits.

    摘要翻译： 一种用于为耐辐射静态随机存取存储器（SRAM）提供消旋电路的方法，包括：提供具有多个配置位的配置存储器; 将读和写电路耦合到配置存储器，用于配置多个配置位; 将辐射硬锁存器耦合到可编程元件，所述辐射硬锁存器控制所述可编程元件; 以及当所述写电路写入所述多个配置位中的至少一个配置位时，提供将所述多个配置位中的至少一个耦合到所述辐射硬锁存器的接口。

    SRAM cell controlled by flash memory cell
    69.
    发明授权
    SRAM cell controlled by flash memory cell 有权
    由闪存单元控制的SRAM单元

    公开(公告)号：US07408815B2

    公开(公告)日：2008-08-05

    申请号：US11740458

    申请日：2007-04-26

    申请人： William C. Plants

    发明人： William C. Plants

    IPC分类号： G11C7/10

    CPC分类号： G11C14/00 ,  G11C11/412 ,  G11C14/0063 ,  H03K19/1776

    摘要： First and second complimentary static random-access-memory cell bit lines are coupled to first and second bit nodes through first and second access transistors controlled by a word line. A first inverter has an input coupled to the first bit node and an output coupled to the second bit node. A second inverter has an input coupled to the second bit node and an output coupled to the first bit node through a first transistor switch. A transistor switch is coupled between the output of a non-volatile memory cell and the first bit node. A control circuit coupled to the gate of the transistor switch. Either the drive level of the non-volatile memory cell is selected to overpower the output of the second inverter or the second inverter is decoupled from the first bit node while the output of the non-volatile memory cell is coupled to the first bit node.

    摘要翻译： 第一和第二互补静态随机存取存储器单元位线通过由字线控制的第一和第二存取晶体管耦合到第一和第二位节点。 第一反相器具有耦合到第一位节点的输入和耦合到第二位节点的输出。 第二反相器具有耦合到第二位节点的输入和通过第一晶体管开关耦合到第一位节点的输出。 晶体管开关耦合在非易失性存储单元的输出和第一位节点之间。 耦合到晶体管开关的栅极的控制电路。 选择非易失性存储单元的驱动电平以使第二反相器的输出过压，或者第二反相器与第一位节点去耦，而非易失性存储单元的输出耦合到第一位节点。