摘要:
A method for forming gate oxide layers of a semiconductor device including defining a first, a second, and a third device region by forming device isolation regions on a semiconductor substrate. The method also includes forming a sacrificing dielectric layer on the substrate, removing the sacrificing dielectric layer on the first device region by selective etching, and forming a first gate oxide layer by oxidizing the first device region. The method further includes removing the sacrificing dielectric layer on the second and third device regions, forming a second gate oxide layer on the second and third device region by oxidizing the substrate, forming a photoresist pattern exposing the third device region and covering the first and second device regions, and forming a third gate oxide layer by oxidizing the third device region.
摘要:
A split gate memory device and fabricating method thereof, wherein gate insulating and polysilicon layers are sequentially formed on a substrate. The polysilicon layer is patterned and a capping insulating layer is formed on portions thereof. A pair of self-aligned control gates having identical bottom widths are formed with a tunnel insulating layer interposed between the control gates and sidewalls of the polysilicon layer pattern and capping insulating layer. The tunnel insulating layer, patterned polysilicon layer and gate insulating layer are selectively etched to expose a portion of the substrate thereby forming a pair of floating gates. Ions are implanted into the exposed substrate and portions of the substrate adjoining the control gates to form a common source region and a drain region, respectively. The capping insulating layer on the floating gate protects an acute section of the tunnel insulating layer from attack during the etching and ion implantation.
摘要:
Disclosed are a chip scale package and a method of fabricating the chip scale package. The chip scale package comprises an insulating layer formed on the upper surface of a chip provided with a plurality of terminals on its one surface, a plurality of conductive layers formed on the insulating layer and spaced from each other by a designated distance so as to be connected to each of a plurality of the terminals, and a plurality of electrode surfaces formed on each of the upper surfaces of a plurality of the conductive layers. The chip scale package is miniaturized in the whole package size. Further, the method of fabricating the chip scale package does not require a wire-bonding step or a via hole forming step, thereby simplifying the fabrication process of the chip scale package and improving the reliability of the chip scale package.
摘要:
The present invention relates to a coating method for the preparation of a coated nuclear fuel. Particularly, the present invention relates to the coating method of nuclear fuel surface with more than two coated layers of carbides, borides or nitrides and their compounds comprising deposition or permeation steps of i) elements or mixture that can form carbides, borides or nitrides and ii) a layer of pyrolytic carbon or boron prepared by chemical vapor deposition(CVD) or sputtering in sequence or in reverse sequence, or nitrogen prepared by gas permeation in sequence, on the nuclear fuel surface. The coated layers are formed with carbides, borides, nitrides or their mixture at high temperature and pressure by a combustion synthesis. The coating method of this invention can be applied to various types of nuclear fuels either in particle or in pellet type and control and preserve fine crystal structure without phase transition since the surface of nuclear fuel coated with pyrolytic carbon and silicon is heated only for several seconds by heat source such as laser beam, arc or microwave. Thus, the present invention is excellent method of coating nuclear fuel surface not only for particle type fuel which used in High Temperature Gas-cooled Reactor (HTGR) but also for pellet type fuel used for Water-cooled Reactors.