公开(公告)号：US20070097926A1

公开(公告)日：2007-05-03

申请号：US10561057

申请日：2003-06-18

Applicant: Sheng Liu ,  Baijun Zhao ,  Jun Hu

Inventor： Sheng Liu ,  Baijun Zhao ,  Jun Hu

IPC: H04B7/216

CPC classification number: H04L47/10 ,  H04L47/14 ,  H04L47/2408 ,  H04L47/2441 ,  H04L47/2458 ,  H04L47/32 ,  H04W28/08 ,  H04W28/18 ,  H04W72/1242 ,  H04W84/04

Abstract: The present invention provides a method for using Differentiated Services (DiffServ) to implement the IP packet classification and the marking of a Differential Service Code Point (DSCP) for the quality of service (QoS) in the wireless access network of the IP-based universal mobile telecommunication system (UMTS). The present invention makes a classification to the data stream which is outgoing from the Iub interface at the Node B side, data stream which is outgoing from the Iub interface at the RNC side and data stream which is outgoing from the Iur interface at the RNC side according to the direction and the process of the respective data streams, and assigns and adjusts the priority of the data stream classified according to the principles for optimizing QoS and radio resources. When the network is congested, the data stream with a high level will have a higher priority than that with a lower level in queue and source occupancy, and the packet with a lower priority in the same queue is discarded. The DiffServ only contains a limited number of service levels and has little condition information, thus easy to be achieved and expanded.

Abstract translation: 本发明提供了一种使用差分服务（DiffServ）来实现IP分组分类和在基于IP的通用无线接入网络中针对服务质量（QoS）的差分服务码点（DSCP）的标记的方法 移动电信系统（UMTS）。 本发明对从节点B侧的Iub接口输出的数据流进行分类，从RNC侧的Iub接口输出的数据流和从RNC侧的Iur接口输出的数据流 根据各个数据流的方向和过程，根据QoS和无线资源的优化原则分配和调整分类的数据流的优先级。 当网络拥塞时，具有高级别的数据流将具有比在队列和源占用中较低级别的优先级更高的优先级，并且丢弃具有较低优先级的分组在同一队列中。 DiffServ仅包含有限数量的服务级别，并且几乎没有条件信息，因此易于实现和扩展。

公开(公告)号：US20170338301A1

公开(公告)日：2017-11-23

申请号：US15162397

申请日：2016-05-23

Applicant: Jun Hu

Inventor： Jun Hu

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/40 ,  H01L21/304 ,  H01L21/266 ,  H01L21/761 ,  H01L21/308 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/66712 ,  H01L21/266 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/761 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/404 ,  H01L29/7811

Abstract: This invention discloses a semiconductor power device formed on an upper epitaxial layer of a first conductivity type supported on a semiconductor substrate comprises an active cell area and a termination area disposed near edges of the semiconductor substrate. The semiconductor power device having a super junction structure with the epitaxial layer formed with a plurality of doped columns of a second conductivity type. The termination area further comprises a plurality of surface guard ring regions of the second conductivity type dispose near a top surface of the epitaxial layer close to the doped columns of the second conductivity type. In one of the embodiments, one of the surface guard ring regions extending laterally over several of the doped columns in the termination area.

公开(公告)号：US09247600B2

公开(公告)日：2016-01-26

申请号：US14529250

申请日：2014-10-31

Applicant: Jun Hu

Inventor： Jun Hu ,  Yongming Deng ,  Ping Liu

IPC: G05F1/00 ,  H05B37/02 ,  H05B39/04 ,  H05B37/00 ,  H05B33/08

CPC classification number: H05B33/0842 ,  Y02B20/42

Abstract: An LED actuating device comprises an LED actuating module, the LED actuating module comprises a micro-programmed control unit (MCU), a VF-value detection module, an actuator and an LED lamp unit; the MCU receives the VF value detected by the VF-value detection module; when the VF value is greater than or equal to a first boundary value, the LED lamp unit is actuated to operate in the constant current area at the first constant actuating current by the actuator; when the VF value is less than the first boundary value, the LED lamp unit is actuated to operate in the regulation area at the continuous step-down actuating current by the actuator until the VF is equal to the second boundary value, and the second boundary value is less than the first boundary value.

Abstract translation: LED驱动装置包括LED驱动模块，LED驱动模块包括微编程控制单元（MCU），VF值检测模块，致动器和LED灯单元; MCU接收VF值检测模块检测到的VF值; 当VF值大于或等于第一边界值时，LED灯单元被致动以在致动器的第一恒定致动电流下在恒定电流区域中操作; 当VF值小于第一边界值时，LED灯单元被致动以在致动器的连续降压致动电流下在调节区域中操作，直到VF等于第二边界值，并且第二边界 值小于第一个边界值。

公开(公告)号：US08896131B2

公开(公告)日：2014-11-25

申请号：US13020758

申请日：2011-02-03

Applicant: Anup Bhalla ,  Sik Lui ,  Jun Hu ,  Fei Wang

Inventor： Anup Bhalla ,  Sik Lui ,  Jun Hu ,  Fei Wang

IPC: H01L23/528 ,  H03K17/10 ,  H03K17/04 ,  H01L27/085 ,  H01L27/06 ,  H03K17/567 ,  H03K17/687

CPC classification number: H03K17/6871 ,  H01L27/0629 ,  H01L27/085 ,  H01L2224/73265 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H03K17/0406 ,  H03K17/102 ,  H03K17/567 ,  H03K2017/6875 ,  H01L2924/00

Abstract: A switching device includes a low voltage normally-off transistor and a control circuit built into a common die. The device includes source, gate and drain electrodes for the transistor and one or more auxiliary electrodes. The drain electrode is on one surface of a die on which the transistor is formed, while each of the remaining electrodes is located on an opposite surface. The one or more auxiliary electrodes provide electrical contact to the control circuit, which is electrically connected to one or more of the other electrodes.

Abstract translation: 开关器件包括低电压常关晶体管和内置在公共管芯中的控制电路。 该器件包括用于晶体管的源极，栅极和漏极以及一个或多个辅助电极。 漏电极在其上形成晶体管的管芯的一个表面上，而每个剩余的电极位于相对的表面上。 一个或多个辅助电极提供与控制电路的电接触，该电接触电连接到一个或多个其它电极。

公开(公告)号：US20140027841A1

公开(公告)日：2014-01-30

申请号：US13561523

申请日：2012-07-30

Applicant: Anup Bhalla ,  Hamza Yilmaz ,  Madhur Bobde ,  Lingpeng Guan ,  Jun Hu ,  Jongoh Kim ,  Yongping Ding

Inventor： Anup Bhalla ,  Hamza Yilmaz ,  Madhur Bobde ,  Lingpeng Guan ,  Jun Hu ,  Jongoh Kim ,  Yongping Ding

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/0634 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor power device formed in a semiconductor substrate comprising a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region supported by a heavily doped region. The semiconductor power device further comprises source trenches opened into the highly doped region filled with conductive trench filling material in electrical contact with the source region near the top surface. The semiconductor power device further comprises buried P-regions disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

公开(公告)号：US08637959B2

公开(公告)日：2014-01-28

申请号：US13220485

申请日：2011-08-29

Applicant: Wensheng Qian ,  Donghua Liu ,  Jun Hu

Inventor： Wensheng Qian ,  Donghua Liu ,  Jun Hu

IPC: H01L21/02

CPC classification number: H01L29/7371 ,  H01L21/76224 ,  H01L21/8249 ,  H01L29/0817 ,  H01L29/161 ,  H01L29/41708 ,  H01L29/66242

Abstract: The invention discloses a vertical parasitic PNP transistor in a BiCMOS process and manufacturing method of the same, wherein an active region is isolated by STIs. The transistor includes a collector region, a base region, an emitter region, pseudo buried layers, and N-type polysilicon. The pseudo buried layers, formed at the bottom of the STIs located on both sides of the collector region, extend laterally into the active region and contact with the collector region, whose electrodes are picked up through making deep-hole contacts in the STIs. The N-type polysilicon is formed on the base region and contacts with it, whose electrodes are picked up through making metal contacts on the N-type polysilicon. The transistors can be used as output devices in high-speed and high-gain circuits, efficiently reducing the transistors area, diminishing the collector resistance, and improving the transistors performance. The method can reduce the cost without additional technological conditions.

Abstract translation: 本发明公开了一种BiCMOS工艺中的垂直寄生PNP晶体及其制造方法，其中有源区由STI分离。 晶体管包括集电极区域，基极区域，发射极区域，伪掩埋层和N型多晶硅。 形成在位于集电区域两侧的STI的底部的伪掩埋层横向延伸到有源区并与集电区接触，该集电极区通过在STI中形成深孔接触来拾取电极。 N型多晶硅形成在基极区上并与其接触，其电极通过在N型多晶硅上形成金属接触来拾取。 晶体管可以用作高速和高增益电路中的输出器件，有效降低晶体管面积，减小集电极电阻，并提高晶体管的性能。 该方法可以降低成本而不需要额外的技术条件。

公开(公告)号：US08598678B2

公开(公告)日：2013-12-03

申请号：US12963242

申请日：2010-12-08

Applicant: Wensheng Qian ,  Jun Hu ,  Donghua Liu

Inventor： Wensheng Qian ,  Jun Hu ,  Donghua Liu

IPC: H01L29/732 ,  H01L21/8228

CPC classification number: H01L29/732 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/66272

Abstract: A parasitic vertical PNP bipolar transistor in BiCMOS process comprises a collector, a base and an emitter. The collector is formed by active region with p-type ion implanting layer (P type well in NMOS). It connects a P-type conductive region, which formed in the bottom region of shallow trench isolation (STI). The collector terminal connection is through the P-type buried layer and the adjacent active region. The base is formed by N type ion implanting layer above the collector which shares a N-type lightly doped drain (NLDD) implanting of NMOS. Its connection is through the N-type poly on the base region. The emitter is formed by the P-type epitaxy layer on the base region with heavy p-type doped, and connected by the extrinsic base region of NPN bipolar transistor device. This invention also includes the fabrication method of this parasitic vertical PNP bipolar transistor in BiCMOS process. And this PNP bipolar transistor can be used as the I/O (input/output) device in high speed, high current and power gain BiCMOS circuits. It also provides a device option with low cost.

Abstract translation: BiCMOS工艺中的寄生垂直PNP双极晶体管包括集电极，基极和发射极。 集电极由具有p型离子注入层（P型阱在NMOS中）的有源区形成。 它连接形成在浅沟槽隔离（STI）的底部区域中的P型导电区域。 集电极端子连接通过P型掩埋层和相邻的有源区。 基极由收集器上方的N型离子注入层形成，其共享NMOS的N型轻掺杂漏极（NLDD）注入。 其连接是通过基底区域上的N型聚合物。 发射极由P型掺杂的P型外延层构成，并由NPN双极晶体管器件的非本征基极区连接。 本发明还包括在BiCMOS工艺中该寄生垂直PNP双极晶体管的制造方法。 该PNP双极晶体管可用作高速，大电流和功率增益BiCMOS电路中的I / O（输入/输出）器件。 它还提供低成本的设备选项。

公开(公告)号：US20120199875A1

公开(公告)日：2012-08-09

申请号：US13020758

申请日：2011-02-03

Applicant: Anup Bhalla ,  Sik Lui ,  Jun Hu ,  Fei Wang

Inventor： Anup Bhalla ,  Sik Lui ,  Jun Hu ,  Fei Wang

IPC: H01L27/085

CPC classification number: H03K17/6871 ,  H01L27/0629 ,  H01L27/085 ,  H01L2224/73265 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H03K17/0406 ,  H03K17/102 ,  H03K17/567 ,  H03K2017/6875 ,  H01L2924/00

Abstract: A switching device includes a low voltage normally-off transistor and a control circuit built into a common die. The device includes source, gate and drain electrodes for the transistor and one or more auxiliary electrodes. The drain electrode is on one surface of a die on which the transistor is formed, while each of the remaining electrodes is located on an opposite surface. The one or more auxiliary electrodes provide electrical contact to the control circuit, which is electrically connected to one or more of the other electrodes.

Abstract translation: 开关器件包括低电压常关晶体管和内置在公共管芯中的控制电路。 该器件包括用于晶体管的源极，栅极和漏极以及一个或多个辅助电极。 漏电极在其上形成晶体管的管芯的一个表面上，而每个剩余的电极位于相对的表面上。 一个或多个辅助电极提供与控制电路的电接触，该电接触电连接到一个或多个其它电极。

公开(公告)号：US20120060726A1

公开(公告)日：2012-03-15

申请号：US13321555

申请日：2010-05-21

Applicant: Yongyao Yao ,  Jun Hu ,  Zhongwei Cao

Inventor： Yongyao Yao ,  Jun Hu ,  Zhongwei Cao

IPC: E05G1/04

CPC classification number: E05B27/0053 ,  E05B27/0007 ,  E05B27/0042 ,  E05B35/12 ,  E05B47/06 ,  E05B63/0069 ,  E05B65/0075 ,  E05C3/042 ,  E05G1/04

Abstract: An emergently openable safe door having a mechanic lock and an electronic lock. The mechanic lock has a shell and a cylindrical plug in the shell. The plug has a primary keyway for a primary key and an emergent keyway for an emergent key. The mechanic lock and an electric lock are able to respectively be opened with a primary key and enter cod normally and be opened with the primary key and a emergent key emergently when the electronic lock thereof malfunctions or an enter code thereof is forgotten.

Abstract translation: 具有机械锁和电子锁的紧急开启的安全门。 机械锁具有外壳和外壳中的圆柱塞。 插头具有用于主键的主键槽和紧急键的紧急键槽。 机械锁和电锁能够分别用主键打开并正常进入，并且当其电子锁故障或其输入代码被忘记时，主键和紧急钥匙突然打开。

公开(公告)号：US20120060571A1

公开(公告)日：2012-03-15

申请号：US13321549

申请日：2010-05-20

Applicant: Yongyao Yu ,  Jun Hu ,  Zhongwei Cao

Inventor： Yongyao Yu ,  Jun Hu ,  Zhongwei Cao

IPC: E05B35/10

CPC classification number: E05B27/0053 ,  E05B27/0007 ,  E05B27/0042 ,  E05B35/12 ,  E05B63/0069 ,  E05C3/042 ,  Y10T70/5788 ,  Y10T70/7446 ,  Y10T70/7458 ,  Y10T70/7463 ,  Y10T70/7565 ,  Y10T70/7605

Abstract: A dual key bi-step lock having a shell and a cylindrical plug in the shell. The plug has a primary keyway and a secondary keyway and at least one set of primary pin stack and at least one set of secondary pin stack between the shell and the plug, respectively coupling with the primary and the secondary keys. a longitudinal stage is formed on a cylindrical surface of the plug. An involute side face extending from the stage to the cylindrical surface of the plug. The primary key is able to dive the plug to a position of first step open at which the stage is stopped by the key pin of the secondary pin stack. The secondary pin stack is unlocked by the secondary key and the plug is able to be further driven to a position of second step open by the primary and the secondary keys from the first step open.

Abstract translation: 双键双向锁具有外壳和外壳中的圆柱塞。 插头具有主键槽和辅助键槽以及分别与主键和副键耦合的壳和插头之间的至少一组主引脚叠层和至少一组次级引脚叠层。 在插头的圆柱形表面上形成纵向台。 从阶段延伸到插头的圆柱形表面的渐开线侧面。 主键能够将插头潜入第一级打开的位置，在该位置，辅助引脚堆叠的键销停止该级。 辅助销堆叠由辅助钥匙解锁，并且插头能够被进一步驱动到第一阶段打开的主键和辅助键的第二阶段打开的位置。