利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

98 条记录 (耗时 0.037 秒)

    METHOD OF PURIFYING FILTER, AND METHOD OF CLEANING OR DRYING OBJECT TO BE TREATED
    62.
    发明申请
    METHOD OF PURIFYING FILTER, AND METHOD OF CLEANING OR DRYING OBJECT TO BE TREATED 有权
    净化过滤器的方法以及要进行处理的清洁或干燥方法

    公开(公告)号：US20130319957A1

    公开(公告)日：2013-12-05

    申请号：US14000361

    申请日：2011-02-18

    申请人： Hiroshi Sugawara ,  Yoshinori Ono

    发明人： Hiroshi Sugawara ,  Yoshinori Ono

    IPC分类号： B01D29/62

    CPC分类号： B01D29/62 ,  B01D46/0068 ,  B01D65/02 ,  B01D2321/18

    摘要： A filter that filters carbon dioxide in the gaseous, liquid or supercritical state is efficiently purified. The carbon dioxide is used to at least clean or dry an object to be treated, or to clean or dry the object to be treated. A method of purifying a filter for filtering carbon dioxide in a gaseous, liquid or supercritical state is provided. The carbon dioxide is used to at least clean or dry the object to be treated, or to clean and dry the object to be treated. According to the method, the filter 13 is purified before the carbon dioxide is filtered in the gaseous, liquid or supercritical state by the filter 13. The filter 13 is purified by allowing carbon dioxide to pass through the filter.

    摘要翻译： 过滤器可以有效地净化气态，液态或超临界状态的二氧化碳过滤器。 二氧化碳用于至少清洁或干燥待处理物体，或清洁或干燥待处理物体。 提供一种净化用于过滤气态，液态或超临界状态的二氧化碳的过滤器的方法。 二氧化碳用于至少清洁或干燥待处理物体，或清洁和干燥待处理物体。 根据该方法，过滤器13在通过过滤器13以气态，液态或超临界状态过滤二氧化碳之前被净化。通过使二氧化碳通过过滤器来净化过滤器13。

    Replacement data storage circuit storing address of defective memory cell
    64.
    发明授权
    Replacement data storage circuit storing address of defective memory cell 失效
    替换数据存储电路存储有缺陷的存储单元的地址

    公开(公告)号：US08055958B2

    公开(公告)日：2011-11-08

    申请号：US12630094

    申请日：2009-12-03

    申请人： Hiroshi Sugawara

    发明人： Hiroshi Sugawara

    IPC分类号： G11C29/00

    CPC分类号： G11C29/846 ,  G11C29/789

    摘要： A replacement data storage circuit stores an address of a defective memory cell. The replacement data storage circuit includes a plurality of word lines, a plurality of bit lines, and a plurality of replacement data memory cells. The replacement data memory cells are connected to the word lines and the bit lines to store an address of a defective memory cell. Each of the word lines is connected to a plurality of replacement data memory cells and each of the bit lines is connected to one replacement data memory cell.

    摘要翻译： 替换数据存储电路存储有缺陷的存储单元的地址。 替换数据存储电路包括多个字线，多个位线和多个替换数据存储单元。 替换数据存储单元连接到字线和位线以存储有缺陷的存储单元的地址。 每个字线连接到多个替换数据存储单元，并且每个位线连接到一个替换数据存储单元。

    Nonvolatile semiconductor memory device and method of writing data into the same
    66.
    发明授权
    Nonvolatile semiconductor memory device and method of writing data into the same 有权
    非易失性半导体存储器件和将数据写入其中的方法

    公开(公告)号：US07643350B2

    公开(公告)日：2010-01-05

    申请号：US12273141

    申请日：2008-11-18

    申请人： Hiroshi Sugawara

    发明人： Hiroshi Sugawara

    IPC分类号： G11C11/34

    CPC分类号： G11C16/12

    摘要： In a nonvolatile semiconductor memory device, a memory cell array has a plurality of nonvolatile memory cells arranged in a matrix. A selecting section selects as selection memory cells, at least two of the plurality of nonvolatile memory cells from the memory cell array. A write section applies to the selection memory cells, a gate voltage which increases step by step, until a threshold voltage of each of the selection memory cells reaches a target threshold voltage, such that the threshold voltage increases step-by-step.

    摘要翻译： 在非易失性半导体存储器件中，存储单元阵列具有以矩阵形式布置的多个非易失性存储单元。 选择部分从存储单元阵列中选择多个非易失性存储器单元中的至少两个作为选择存储单元。 写入部分适用于选择存储器单元，栅极电压逐步增加，直到每个选择存储单元的阈值电压达到目标阈值电压，使得阈值电压逐步增加。

    Nonvolatile semiconductor memory device and method of testing thereof
    67.
    发明授权
    Nonvolatile semiconductor memory device and method of testing thereof 有权
    非易失性半导体存储器件及其测试方法

    公开(公告)号：US07489573B2

    公开(公告)日：2009-02-10

    申请号：US11806315

    申请日：2007-05-31

    申请人： Hiroshi Sugawara

    发明人： Hiroshi Sugawara

    IPC分类号： G11C7/00

    CPC分类号： G11C29/50 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/30

    摘要： A method of testing a nonvolatile semiconductor memory device is provided. The nonvolatile semiconductor memory device is provided with a memory cell of a field effect transistor type. The method includes: (A) performing erasing of the memory cell by using FN (Fowler-Nordheim) method; (B) performing programming back of the memory cell by using FN method, after the (A) step.

    摘要翻译： 提供一种测试非易失性半导体存储器件的方法。 非易失性半导体存储器件设置有场效应晶体管型的存储单元。 该方法包括：（A）使用FN（Fowler-Nordheim）方法擦除存储器单元; （B）在（A）步骤之后，使用FN方法对存储单元进行编程。

    Semiconductor memory device capable of carrying out stable operation
    68.
    发明授权
    Semiconductor memory device capable of carrying out stable operation 有权
    能够进行稳定运行的半导体存储器件

    公开(公告)号：US07289367B2

    公开(公告)日：2007-10-30

    申请号：US11101410

    申请日：2005-04-08

    申请人： Hiroshi Sugawara

    发明人： Hiroshi Sugawara

    IPC分类号： G11C11/34 ,  G11C16/06 ,  G11C7/00 ,  G11C8/18

    CPC分类号： G11C8/14 ,  G11C8/10 ,  G11C8/18

    摘要： A semiconductor memory device includes a word drive line, and a word line connected with memory cells. A first drive circuit drives the word drive line to a first voltage based on a main word signal, and resets the word drive line to a ground voltage in a time period for transition of an address signal. A second drive circuit outputs a signal of the first voltage to the word line based on a sub-word signal such that a data is read out from one of the memory cells. The main word signal and the sub-word signal are obtained from an address signal, and are signals taking the ground voltage or a second voltage which is lower than the first voltage.

    摘要翻译： 半导体存储器件包括字驱动线和与存储器单元连接的字线。 第一驱动电路基于主字信号将字驱动线驱动到第一电压，并且在用于地址信号的转换的时间段内将字驱动线重置为接地电压。 第二驱动电路基于子字信号将字第一电压的信号输出到字线，使得从存储单元之一读出数据。 主字信号和子字信号是从地址信号获得的，是接地电压的信号或低于第一电压的第二电压。

    Semiconductor memory device with bus driver circuit configured to transfer an output on a common bus onto an output bus with inversion or no inversion
    70.
    发明授权
    Semiconductor memory device with bus driver circuit configured to transfer an output on a common bus onto an output bus with inversion or no inversion 有权
    具有总线驱动器电路的半导体存储器件被配置为将公共总线上的输出转换成具有反转或不反转的输出总线

    公开(公告)号：US07243180B2

    公开(公告)日：2007-07-10

    申请号：US11090357

    申请日：2005-03-28

    申请人： Hiroshi Sugawara

    发明人： Hiroshi Sugawara

    IPC分类号： G11C11/409 ,  G11C11/419 ,  G11C16/06 ,  G11C11/4063 ,  G11C11/413 ,  G06F138/00

    CPC分类号： G11C7/1051 ,  G11C7/062 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/14 ,  G11C7/18 ,  G11C16/26

    摘要： A semiconductor memory device includes first to third data buses, and first and second connection circuits. The first connection circuit inverts and transfers a first output signal on the first data bus read out from a memory onto the second data bus in response to a first selection signal, inverts and transfers a second output signal on the second data bus read out from the memory onto the first data bus in response to a second selection signal, and connects the first and second data buses in response to a reset signal. The second connection circuit inverts and transfers the inverted first output signal on the second data bus onto the third data bus in response to the first selection signal and transfers the second output signal on the second data bus onto the third data bus in response to the second selection signal.

    摘要翻译： 半导体存储器件包括第一至第三数据总线以及第一和第二连接电路。 第一连接电路响应于第一选择信号将从存储器读出的第一数据总线上的第一输出信号反转并传送到第二数据总线上，在从第二数据总线读出的第二数据总线上反转并传送第二输出信号 存储器响应于第二选择信号在第一数据总线上，并且响应于复位信号连接第一和第二数据总线。 第二连接电路响应于第一选择信号将第二数据总线上的反相第一输出信号反转并传送到第三数据总线上，并响应于第二数据总线将第二数据总线上的第二输出信号传送到第三数据总线上 选择信号。