公开(公告)号：US07227239B2

公开(公告)日：2007-06-05

申请号：US10948773

申请日：2004-09-23

申请人： Wagdi William Abadeer ,  John Atkinson Fifield ,  Robert J. Gauthier, Jr. ,  William Robert Tonti

发明人： Wagdi William Abadeer ,  John Atkinson Fifield ,  Robert J. Gauthier, Jr. ,  William Robert Tonti

IPC分类号： H01L29/00 ,  H01L21/44

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A resettable fuse device is fabricated on one surface of a semiconductor substrate (10) and includes: a gate region (20) having first and second ends; a source node (81) formed in proximity to the first end of the gate region; an extension region (52) formed to connect the source node to the first end of the gate region; and a drain node (80) formed in proximity to the second end of the gate region and separated from the gate region by a distance (D) such that upon application of a predetermined bias voltage to the drain node a connection between the drain node and the second end of the gate region is completed by junction depletion. A gate dielectric (30) and a gate electrode (40) are formed over the gate region. Current flows between the source node and the drain node when the predetermined bias is applied to both the drain node and the gate electrode.

摘要翻译： 在半导体衬底（10）的一个表面上制造可重置熔丝器件，并且包括：具有第一和第二端的栅极区域（20） 源极节点（81），其形成在所述栅极区域的第一端附近; 形成为将源极节点连接到栅极区域的第一端的延伸区域（52） 以及漏极节点（80），其形成在栅极区域的第二端附近，并且与栅极区分离距离（D），使得在向漏极节点施加预定的偏置电压时，漏极节点和 栅极区域的第二端通过结损耗完成。 栅极电介质（30）和栅电极（40）形成在栅极区域上方。 当预定偏压施加到漏极节点和栅电极时，电流在源节点和漏极节点之间流动。

公开(公告)号：US06693843B1

公开(公告)日：2004-02-17

申请号：US10318795

申请日：2002-12-13

申请人： Thomas M. Maffitt ,  Russell J. Houghton ,  Mark David Jacunski ,  William Robert Tonti ,  Kevin McStay

发明人： Thomas M. Maffitt ,  Russell J. Houghton ,  Mark David Jacunski ,  William Robert Tonti ,  Kevin McStay

IPC分类号： G11C800

CPC分类号： G11C8/08

摘要： An apparatus and method for wordline voltage compensation in integrated memories is provided, where the apparatus includes an array threshold voltage (“VT”) monitor, a wordline on voltage (“Vpp”) generator in signal communication with the threshold voltage monitor for providing a wordline on voltage responsive to a change in the monitored array threshold voltage, and a wordline off voltage (“VWLL”) generator in signal communication with the threshold voltage monitor for providing a wordline off voltage responsive to a change in the monitored array threshold voltage; and where the corresponding method for compensating each of a wordline on signal and a wordline off signal in correspondence with an array threshold signal includes monitoring an array threshold signal, generating a wordline on signal responsive to the monitored array threshold signal, and generating a wordline off signal responsive to the monitored array threshold signal.

摘要翻译： 提供了一种用于集成存储器中的字线电压补偿的装置和方法，其中装置包括阵列阈值电压（“VT”）监视器，与阈值电压监视器进行信号通信的电压（“Vpp”）发生器的字线，用于提供 响应于所监视的阵列阈值电压的变化的字线电压以及与阈值电压监视器进行信号通信的字线关断电压（“VWLL”）发生器，用于响应于所监视的阵列阈值电压的变化提供字线关断电压; 并且其中用于补偿与阵列阈值信号相对应的信号上的字线和字线关闭信号中的每一个的相应方法包括监视阵列阈值信号，响应于所监视的阵列阈值信号产生信号上的字线，并产生字线关闭 响应于监视的阵列阈值信号的信号。

公开(公告)号：US06577156B2

公开(公告)日：2003-06-10

申请号：US09731147

申请日：2000-12-05

申请人： Darren L. Anand ,  John Edward Barth, Jr. ,  John Atkinson Fifield ,  Pamela Sue Gillis ,  Peter O. Jakobsen ,  Douglas Wayne Kemerer ,  David E. Lackey ,  Steven Frederick Oakland ,  Michael Richard Ouellette ,  William Robert Tonti

发明人： Darren L. Anand ,  John Edward Barth, Jr. ,  John Atkinson Fifield ,  Pamela Sue Gillis ,  Peter O. Jakobsen ,  Douglas Wayne Kemerer ,  David E. Lackey ,  Steven Frederick Oakland ,  Michael Richard Ouellette ,  William Robert Tonti

IPC分类号： G11C700

CPC分类号： G11C29/80 ,  G11C29/802

摘要： A method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox allows a reduction in the number of fuses required to repair or customize an integrated circuit and allows fuses to be grouped outside of the macros repaired by the fuses. The remote location of fuses allows flexibility in the placement of macros having redundant repair capability, as well as a preferable grouping of fuses for both programming convenience and circuit layout facilitation. The fuses are arranged in rows and columns and represent control words and run-length compressed data to provide a greater quantity of repair points per fuse. The data can be loaded serially into shift registers and shifted to the macro locations to control the selection of redundant circuits to repair integrated circuits having defects or to customize logic.

公开(公告)号：US07985643B2

公开(公告)日：2011-07-26

申请号：US12052855

申请日：2008-03-21

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven J. Holmes ,  David Vaclav Horak ,  Charles William Koburger, III ,  William Robert Tonti

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven J. Holmes ,  David Vaclav Horak ,  Charles William Koburger, III ,  William Robert Tonti

IPC分类号： H01L21/8238

CPC分类号： H01L21/76897 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/28114

摘要： A semiconductor structure. The structure includes (a) a semiconductor layer including a channel region disposed between first and second S/D regions; (b) a gate dielectric region on the channel region; (c) a gate region on the gate dielectric region and electrically insulated from the channel region by the gate dielectric region; (d) a protection umbrella region on the gate region, wherein the protection umbrella region comprises a first dielectric material, and wherein the gate region is completely in a shadow of the protection umbrella region; and (e) a filled contact hole (i) directly above and electrically connected to the second S/D region and (ii) aligned with an edge of the protection umbrella region, wherein the contact hole is physically isolated from the gate region by an inter-level dielectric (ILD) layer which comprises a second dielectric material different from the first dielectric material.

摘要翻译： 半导体结构。 该结构包括（a）包括设置在第一和第二S / D区之间的沟道区的半导体层; （b）沟道区上的栅介质区; （c）栅极电介质区域上的栅极区域，并且通过栅极电介质区域与沟道区域电绝缘; （d）栅极区域上的保护伞区域，其中保护伞区域包括第一介电材料，并且其中栅极区域完全处于保护伞区域的阴影中; 和（e）直接在第二S / D区域上方并电连接到第二S / D区域的填充接触孔（i）和（ii）与保护伞区域的边缘对准，其中接触孔通过一个 层间介电层（ILD）层，其包括不同于第一介电材料的第二电介质材料。

公开(公告)号：US20090278201A1

公开(公告)日：2009-11-12

申请号：US12116237

申请日：2008-05-07

申请人： Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed Hickory Rankin ,  Robert R. Robison ,  William Robert Tonti

发明人： Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed Hickory Rankin ,  Robert R. Robison ,  William Robert Tonti

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/78654 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/78603

摘要： Field effect transistor and methods of fabricating field effect transistors. The field effect transistors includes: a semiconductor substrate; a silicon oxide layer on the substrate; a stiffening layer on the silicon oxide layer; a single crystal silicon layer on the stiffening layer; a source and a drain on opposite sides of a channel region of the silicon layer; a gate electrode over the channel region and a gate dielectric between the gate electrode and the channel region.

摘要翻译： 场效应晶体管和制造场效应晶体管的方法。 场效应晶体管包括：半导体衬底; 衬底上的氧化硅层; 氧化硅层上的加强层; 加强层上的单晶硅层; 在硅层的沟道区的相对侧上的源极和漏极; 沟道区上的栅极电极和栅电极和沟道区之间的栅极电介质。

公开(公告)号：US07473904B2

公开(公告)日：2009-01-06

申请号：US12028850

申请日：2008-02-11

申请人： Wagdi William Abadeer ,  Ethan Harrison Cannon ,  Dennis Thomas Cox ,  William Robert Tonti

发明人： Wagdi William Abadeer ,  Ethan Harrison Cannon ,  Dennis Thomas Cox ,  William Robert Tonti

IPC分类号： H01L31/00

CPC分类号： G01T1/244

摘要： A device and system for monitoring ionizing radiation. The device including: a diode formed in a silicon layer below an oxide layer buried below a surface of a silicon substrate; and a cathode of the diode coupled to a precharged node of a clocked logic circuit, an output state of the clocked logic circuit responsive a change in state of the precharged node, a state of the precharged node responsive to ionizing radiation induced charge collected by a depletion region of the diode and collected in the cathode.

摘要翻译： 用于监测电离辐射的装置和系统。 该器件包括：二极管，其形成在埋在硅衬底的表面下方的氧化物层下方的硅层中; 并且二极管的阴极耦合到时钟逻辑电路的预充电节点，时钟逻辑电路的输出状态响应于预充电节点的状态改变，预充电节点的状态响应于电离辐射诱发的电荷 二极管的耗尽区域并收集在阴极中。

公开(公告)号：US20090001481A1

公开(公告)日：2009-01-01

申请号：US11768270

申请日：2007-06-26

申请人： Ethan Harrison Cannon ,  Toshiharu Furukawa ,  David Vaclav Horak ,  Jack A. Mandelman ,  William Robert Tonti

发明人： Ethan Harrison Cannon ,  Toshiharu Furukawa ,  David Vaclav Horak ,  Jack A. Mandelman ,  William Robert Tonti

IPC分类号： H01L27/105 ,  H01L21/8238

CPC分类号： H01L27/0733 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L28/40

摘要： A semiconductor structure and a method for forming the same. The semiconductor structure includes (a) a semiconductor substrate, (b) a shallow trench isolation (STI) region on the semiconductor substrate, and (c) a first semiconductor transistor on the semiconductor substrate. The first semiconductor transistor includes (I) a first source/drain region, (ii) a second source/drain region, and (iii) a first gate electrode region. The first and second source/drain regions are doped with a same doping polarity. The semiconductor structure further includes a first doped region in the semiconductor substrate. The first doped region is on a first side wall and a bottom wall of the STI region. The first doped region is in direct physical contact with the second source/drain region. The first doped region and the second source/drain region are doped with a same doping polarity.

摘要翻译： 半导体结构及其形成方法。 半导体结构包括（a）半导体衬底，（b）半导体衬底上的浅沟槽隔离（STI）区域，以及（c）半导体衬底上的第一半导体晶体管。 第一半导体晶体管包括（I）第一源极/漏极区域，（ii）第二源极/漏极区域，以及（iii）第一栅极电极区域。 第一和第二源/漏区掺杂相同的掺杂极性。 半导体结构还包括在半导体衬底中的第一掺杂区域。 第一掺杂区域位于STI区域的第一侧壁和底壁上。 第一掺杂区域与第二源极/漏极区域直接物理接触。 第一掺杂区域和第二源极/漏极区域掺杂相同的掺杂极性。

公开(公告)号：US07375339B2

公开(公告)日：2008-05-20

申请号：US11380736

申请日：2006-04-28

申请人： Wagdi William Abadeer ,  Ethan Harrison Cannon ,  Dennis Thomas Cox ,  William Robert Tonti

发明人： Wagdi William Abadeer ,  Ethan Harrison Cannon ,  Dennis Thomas Cox ,  William Robert Tonti

IPC分类号： G01T1/02

CPC分类号： G01T1/244

摘要： A method, device and system for monitoring ionizing radiation. The method including: collecting an ionizing radiation induced charge collected by the depletion region of a diode formed in a silicon layer below an oxide layer buried below a surface of a silicon substrate; and coupling a cathode of the diode to a precharged node of a clocked logic circuit such that the ionizing radiation induced charge collected by a depletion region of the diode will discharge the precharged node and change an output state of the clocked logic circuit.

摘要翻译： 一种用于监测电离辐射的方法，装置和系统。 该方法包括：收集由埋在硅衬底表面下方的氧化物层下面的硅层中形成的二极管的耗尽区收集的电离辐射感应电荷; 以及将二极管的阴极耦合到时钟逻辑电路的预充电节点，使得由二极管的耗尽区收集的电离辐射感应电荷将放电预充电节点并改变时钟逻辑电路的输出状态。

公开(公告)号：US5937289A

公开(公告)日：1999-08-10

申请号：US3106

申请日：1998-01-06

申请人： Gary Bela Bronner ,  Jeffrey P. Gambino ,  Jack A. Mandelman ,  Carl J. Radens ,  William Robert Tonti

发明人： Gary Bela Bronner ,  Jeffrey P. Gambino ,  Jack A. Mandelman ,  Carl J. Radens ,  William Robert Tonti

IPC分类号： H01L21/225 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L21/8238

CPC分类号： H01L21/28035 ,  H01L21/82345

摘要： Dual work function doping is provided by doping a selected number of gate structures having self-aligned insulating layer on top of the structures through at least one side wall of the gate structures with a first conductivity type to thereby provide an array of gate structures whereby some are doped with the first conductivity type and others of the gate structures are doped with a second and different conductivity type. Also provided is an array of gate structures whereby the individual gate structures contain self-aligned insulating layer on their top portion and wherein some of the gate structures are doped with a first conductivity type and other of the gate structures are doped with a second and different conductivity type.

摘要翻译： 通过在第一导电类型的栅极结构的至少一个侧壁上掺杂选定数量的具有自对准绝缘层的栅极结构的结构，从而提供栅极结构的阵列，从而提供一些 掺杂有第一导电类型，并且其他栅极结构被掺杂有第二和不同的导电类型。 还提供了栅极结构的阵列，其中各个栅极结构在其顶部部分上包含自对准的绝缘层，并且其中一些栅极结构被掺杂有第一导电类型，并且其他栅极结构被掺杂有第二和不同的 导电类型。

公开(公告)号：US20090113357A1

公开(公告)日：2009-04-30

申请号：US11923784

申请日：2007-10-25

申请人： Wagdi William Abadeer ,  Ethan Harrison Cannon ,  Dennis Thomas Cox ,  William Robert Tonti

发明人： Wagdi William Abadeer ,  Ethan Harrison Cannon ,  Dennis Thomas Cox ,  William Robert Tonti

IPC分类号： G06F17/50

CPC分类号： H01L31/103 ,  G11C5/005 ,  G11C11/4125 ,  H01L31/115 ,  H01L31/118 ,  H03K19/0033

摘要： A method, device and system for monitoring ionizing radiation, and design structures for ionizing radiation monitoring devices. The method including: collecting an ionizing radiation induced charge collected by the depletion region of a diode formed in a silicon layer below an oxide layer buried below a surface of a silicon substrate; and coupling a cathode of the diode to a precharged node of a clocked logic circuit such that the ionizing radiation induced charge collected by a depletion region of the diode will discharge the precharged node and change an output state of the clocked logic circuit.

摘要翻译： 用于监测电离辐射的方法，装置和系统，以及用于电离辐射监测装置的设计结构。 该方法包括：收集由埋在硅衬底表面下方的氧化物层下面的硅层中形成的二极管的耗尽区收集的电离辐射感应电荷; 以及将二极管的阴极耦合到时钟逻辑电路的预充电节点，使得由二极管的耗尽区收集的电离辐射感应电荷将放电预充电节点并改变时钟逻辑电路的输出状态。