公开(公告)号：US20240379136A1

公开(公告)日：2024-11-14

申请号：US18314153

申请日：2023-05-09

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Chih-Wei Hu

IPC: G11C7/06 ,  G11C5/06 ,  G11C16/08 ,  H01L23/00 ,  H01L25/065 ,  H10B41/20 ,  H10B41/40 ,  H10B43/20 ,  H10B43/40 ,  H10B80/00

Abstract: A memory device, such as a three-dimensional AND or NOR flash memory, includes a first chip and a second chip. The first chip has multiple source line switches, multiple bit line switches, multiple page buffers, and multiple sensing amplifiers. The first chip has multiple first pads. The second chip has multiple memory cells to form multiple memory cell blocks. Multiple second pads are on a first surface of the second chip to be respectively coupled to multiple local bit lines and multiple local source lines of the memory cell blocks. Each of the first pads is coupled to the corresponding second pads.

公开(公告)号：US12094568B2

公开(公告)日：2024-09-17

申请号：US17866958

申请日：2022-07-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue

IPC: G11C7/10 ,  G11C7/12 ,  G11C8/08 ,  G11C15/04

CPC classification number: G11C7/1096 ,  G11C7/1069 ,  G11C7/12 ,  G11C8/08 ,  G11C15/04

Abstract: A memory array is arranged to store data words in respective sets of TCAM cells, where each TCAM cell is configured to store ternary states of a bit of the stored word. A circuit to select a set of TCAM cells in the set of TCAM cells, such as decoders and drivers for word lines, bit lines, block select gates. A circuit to apply an input search word to the TCAM cells in the selected set of TCAM cells, such as a search word buffer or driver on one of word lines or bit lines for the array. A circuit to generate an output indicating similarity of the stored word in the selected set of TCAM cells to the input search word, based on mismatch or possible mismatch of more than one bit of the search word.

公开(公告)号：US12052869B2

公开(公告)日：2024-07-30

申请号：US17475932

申请日：2021-09-15

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh ,  Hang-Ting Lue

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A three-dimensional AND flash memory device includes a stack structure, isolators, channel pillars, source pillars and drain pillars, and charge storage structures. The stack structure is located on a dielectric substrate and includes gate layers and insulating layers alternately stacked with each other. The isolators divide the stack structure into sub-blocks and include walls and slits. The walls include isolation layers and the insulating layers stacked alternately with each other, and the isolation layers are buried in the gate layers. The slits alternate with the walls, and each of the slits extends through the stack structure. The channel pillars extend through the stack structure in each of the sub-blocks. The source pillars and the drain pillars are located in the channel pillars. The charge storage structures are located between the gate layers and the channel pillar.

公开(公告)号：US20240221855A1

公开(公告)日：2024-07-04

申请号：US18149676

申请日：2023-01-04

Applicant: MACRONIX International Co, Ltd.

Inventor： Chih-Wei Hu ,  Teng Hao Yeh ,  Hang-Ting Lue

IPC: G11C29/12 ,  G11C16/26

CPC classification number: G11C29/1201 ,  G11C16/26 ,  G11C2029/1204

Abstract: A memory device and a test method thereof are provided. The memory device (e.g., a 3D stack AND type flash memory) includes a memory cell array, a first global bit line, a second global bit line, and a switch component. The memory cell array is divided into a first memory cell group and a second memory cell group. The first memory cell group has a plurality of first local bit lines and a plurality of first local source lines, and the second memory cell group has a plurality of second local bit lines and a plurality of second local source lines. The switch component is configured to couple the first local source lines to a common source line or couple the second local source lines to the common source line during a plurality of different test modes.

公开(公告)号：US11985822B2

公开(公告)日：2024-05-14

申请号：US17009968

申请日：2020-09-02

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao Yeh ,  Chih-Wei Hu ,  Hang-Ting Lue ,  Guan-Ru Lee

IPC: H01L27/115 ,  H01L23/522 ,  H01L23/535 ,  H01L27/11565 ,  H01L27/11582 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B43/10

Abstract: A memory device is provided. The memory device includes a stacked structure, a tubular element, a conductive pillar and memory cells. The tubular element includes a dummy channel layer and penetrates the stacked structure. The conductive pillar is enclosed by the tubular element and extending beyond a bottom surface of the dummy channel layer. The memory cells are in the stacked structure and electrically connected to the conductive pillar.

公开(公告)号：US20230377633A1

公开(公告)日：2023-11-23

申请号：US17751445

申请日：2022-05-23

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Shang-Chi Yang ,  Fu-Nian Liang ,  Ken-Hui Chen ,  Chun-Hsiung Hung

IPC: G11C11/4094 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4072 ,  G11C11/4091 ,  G11C11/4093 ,  G11C5/06

CPC classification number: G11C11/4094 ,  G11C11/4085 ,  G11C11/4096 ,  G11C11/4072 ,  G11C11/4091 ,  G11C11/4093 ,  G11C5/063

Abstract: A three dimension memory device, such as an AND-type memory, includes a memory cell tile, multiple source line switches, multiple first bit line switches to fourth bit line switches. The memory cell tile is divided into a first and a second memory cell sub-tiles. The first bit line switches are respectively coupled to multiple first bit lines of a first part of the first memory cell sub-tile. The second bit line switches are respectively coupled to multiple second bit lines of a second part of the first memory cell sub-tile. The third bit line switches are respectively coupled to multiple third bit lines of a first part of the second memory cell sub-tile. The fourth bit line switches are respectively coupled to multiple fourth bit lines of a second part of the second memory cell sub-tile.

公开(公告)号：US20230269944A1

公开(公告)日：2023-08-24

申请号：US18308594

申请日：2023-04-27

Applicant: MACRONIX International Co., Ltd.

Inventor： Hang-Ting Lue ,  Wei-Chen Chen ,  Teng-Hao Yeh ,  Guan-Ru Lee

IPC: H10B43/27 ,  H01L23/528 ,  H10B43/10

CPC classification number: H10B43/27 ,  H01L23/528 ,  H10B43/10 ,  H01L21/0217

Abstract: Provided are a 3D flash memory and an array layout thereof. The 3D flash memory includes a gate stack structure, a annular channel pillar, a first source/drain pillar, a second source/drain pillar and a charge storage structure. The gate stack structure is disposed on a dielectric base and includes a plurality of gate layers electrically insulated from each other. The annular channel pillar is disposed on the dielectric base and penetrates through the gate stack structure. The first source/drain pillar and the second source/drain pillar are disposed on the dielectric base, are located within the channel pillar and penetrate through the gate stack structure. The first source/drain pillar and the second source/drain pillar are separated from each other and are each connected to the channel pillar. The charge storage structure is disposed between each of the plurality of gate layers and the channel pillar.

公开(公告)号：US20230134957A1

公开(公告)日：2023-05-04

申请号：US17569419

申请日：2022-01-05

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue

IPC: G11C16/10 ,  G11C16/04 ,  G11C5/02 ,  H01L23/34

Abstract: A 3D flash memory module chip includes a memory chip and a control chip. The memory chip includes a plurality of tiles and a plurality of heaters. The tiles each include a plurality of 3D flash memory structures. The heaters are disposed around the 3D flash memory structures of each of the tiles. The control chip is bonded with the memory chip to drive at least one of the heaters.

公开(公告)号：US20230070119A1

公开(公告)日：2023-03-09

申请号：US17695943

申请日：2022-03-16

Applicant: Macronix International Co., Ltd.

Inventor： Hang-Ting Lue ,  Wei-Chen Chen ,  Teng-Hao Yeh

IPC: H01L27/11

Abstract: Methods, devices, systems, and apparatus for three-dimensional semiconductor structures are provided. In one aspect, a semiconductor device includes: a semiconductor substrate, multiple conductive layers vertically stacked on the semiconductor substrate, and multiple transistors. The multiple conductive layers include a first conductive layer, a second conductive layer, and a third conductive layer that are sequentially stacked together. The multiple transistors include a first transistor and a second transistor in the first conductive layer and a third transistor in the third conductive layer. Each transistor includes a first terminal, a second terminal, and a gate terminal. First terminals of the first, second, and third transistors are conductively coupled to a first conductive node in the second conductive layer.

公开(公告)号：US20220293628A1

公开(公告)日：2022-09-15

申请号：US17249701

申请日：2021-03-10

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen Chen ,  Hang-Ting Lue

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  G11C16/30 ,  G11C16/26 ,  G11C16/14

Abstract: A memory device includes a stack and a plurality of memory strings respectively penetrating the stack along the first direction and including adjacent ones of the first memory string and the second memory string. The first memory string and the second memory string include conductive pillars (including first to third conductive pillars), channel structures, and memory structures. The first memory string and the second memory string share the second conductive pillar. The channel structures include first to fourth channel layers respectively extending along the first direction. The first channel layer and the second channel layer correspond to the first memory string and are separated from each other. The third channel layer and the fourth channel layer correspond to the second memory string and are separated from each other. The memory structures are disposed between the stack and the channel structures.