公开(公告)号：US10923480B2

公开(公告)日：2021-02-16

申请号：US16409010

申请日：2019-05-10

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Litao Yang ,  Gurtej S. Sandhu ,  Richard J. Hill

IPC: H01L29/06 ,  H01L23/528 ,  H01L21/768 ,  H01L21/762 ,  H01L29/66 ,  H01L27/108 ,  H01L21/02 ,  H01L21/311 ,  H01L21/306 ,  H01L23/532

Abstract: Systems, apparatuses, and methods related to capacitance reduction in a semiconductor device are described. An example method may include forming an oxide only spacer over a portion of a sense line, formed on a semiconductor substrate, to separate the sense line from a storage node contact region of a semiconductor device and to reduce a capacitance between the sense line and the storage node contact region. The method may further include forming the storage node contact region in an active area of the semiconductor device neighboring the sense line and conductively connecting the sense line to the storage node contact region to enable a storage node to be sensed by the sense line.

公开(公告)号：US20200321351A1

公开(公告)日：2020-10-08

申请号：US16374527

申请日：2019-04-03

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Francois H. Fabreguette ,  Richard J. Hill ,  Purnima Narayanan ,  Shyam Surthi

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/02 ,  G11C16/08

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have conductive terminal ends within control gate regions. The control gate regions are vertically spaced from one another by first insulative regions which include first insulative material. Charge-storage material is laterally outward of the conductive terminal ends, and is configured as segments. The segments of the charge-storage material are arranged one atop another and are vertically spaced from one another by second insulative regions which include second insulative material. The second insulative material has a different dielectric constant than the first insulative material. Charge-tunneling material extends vertically along the stack, and is adjacent to the segments of the charge-trapping material. Channel material extends vertically along the stack, and is adjacent to the charge-tunneling material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20200287003A1

公开(公告)日：2020-09-10

申请号：US16294759

申请日：2019-03-06

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Deepak Chandra Pandey ,  Haitao Liu ,  Richard J. Hill ,  Guangyu Huang ,  Yunfei Gao ,  Ramanathan Gandhi ,  Scott E. Sills

IPC: H01L29/267 ,  H01L29/786 ,  H01L29/16 ,  H01L29/207 ,  H01L29/08 ,  H01L27/108

Abstract: Some embodiments include an integrated assembly having a polycrystalline first semiconductor material, and having a second semiconductor material directly adjacent to the polycrystalline first semiconductor material. The second semiconductor material is of a different composition than the polycrystalline first semiconductor material. A conductivity-enhancing dopant is within the second semiconductor material. The conductivity-enhancing dopant is a neutral-type dopant relative to the polycrystalline first semiconductor material. An electrical gate is adjacent to a region of the polycrystalline first semiconductor material and is configured to induce an electric field within said region of the polycrystalline first semiconductor material. The gate is not adjacent to the second semiconductor material.

公开(公告)号：US20200066578A1

公开(公告)日：2020-02-27

申请号：US16531837

申请日：2019-08-05

Applicant: Micron Technology, Inc.

Inventor： Scott L. Light ,  Richard J. Hill

IPC: H01L21/768 ,  H01L21/033 ,  H01L23/528 ,  H01L23/522

Abstract: A metal pattern comprising interconnected small metal segments, medium metal segments, and large metal segments. At least one of the small metal segments comprises a pitch of less than about 45 nm and the small metal segments, medium metal segments, and large metal segments are separated from one another by variable spacing. Semiconductor devices comprising initial metallizations, systems comprising the metal pattern, and methods of forming a pattern are also disclosed.

公开(公告)号：US20180323212A1

公开(公告)日：2018-11-08

申请号：US16031919

申请日：2018-07-10

Applicant: Micron Technology, Inc.

Inventor： David Daycock ,  Richard J. Hill ,  Christopher Larsen ,  Woohee Kim ,  Justin B. Dorhout ,  Brett D. Lowe ,  John D. Hopkins ,  Qian Tao ,  Barbara L. Casey

IPC: H01L27/11582 ,  H01L29/423 ,  H01L21/28 ,  H01L27/1157 ,  H01L29/10

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L29/1037 ,  H01L29/4234 ,  H01L29/7926

Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.

公开(公告)号：US10083981B2

公开(公告)日：2018-09-25

申请号：US15422335

申请日：2017-02-01

Applicant: Micron Technology, Inc.

Inventor： David Daycock ,  Richard J. Hill ,  Christopher Larsen ,  Woohee Kim ,  Justin B. Dorhout ,  Brett D. Lowe ,  John D. Hopkins ,  Qian Tao ,  Barbara L. Casey

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  H01L21/28 ,  H01L29/10

Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.

公开(公告)号：US20250132248A1

公开(公告)日：2025-04-24

申请号：US19005952

申请日：2024-12-30

Applicant: Micron Technology, Inc.

Inventor： David H. Wells ,  Richard J. Hill ,  Umberto M. Meotto ,  Matthew Thorum

IPC: H01L23/522 ,  G11C16/04 ,  H01L23/528 ,  H01L23/532 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A microelectronic device comprises a stack structure overlying a source tier. The stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The microelectronic device comprises a staircase structure within the stack structure and having steps comprising lateral edges of the tiers, support structures vertically extending through the stack structure and within a horizontal area of the staircase structure, and conductive contacts vertically extending through the stack structure and horizontally neighboring the support structures within the horizontal area of the staircase structure. Each of the conductive contacts has a horizontally projecting portion in contact with one of the conductive structures of the stack structure at one of the steps of the staircase structure. Related memory devices, electronic systems, and methods of forming the microelectronic devices are also described.

公开(公告)号：US11864386B2

公开(公告)日：2024-01-02

申请号：US17837879

申请日：2022-06-10

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Richard J. Hill ,  Yi Fang Lee ,  Martin C. Roberts

IPC: H10B43/27 ,  H10B51/00 ,  H10B53/20 ,  G06F3/06

CPC classification number: H10B43/27 ,  G06F3/0688 ,  H10B51/00 ,  H10B53/20

Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. The individual memory cells comprise a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode electrically couples to the first source/drain region. Wordline structures extend elevationally through the insulative material and the memory cells of the vertically-alternating tiers. Individual of the gates that are in different of the memory cell tiers directly electrically couple to individual of the wordline structures. Sense-lines electrically couple to multiple of the second source/drain regions of individual of the transistors. Other embodiments are disclosed.

公开(公告)号：US11735672B2

公开(公告)日：2023-08-22

申请号：US17216269

申请日：2021-03-29

Applicant: Micron Technology, Inc.

Inventor： Aaron Michael Lowe ,  Zhuo Chen ,  Marko Milojevic ,  Timothy A. Quick ,  Richard J. Hill ,  Scott E. Sills

IPC: H01L29/786 ,  H01L27/13 ,  H01L27/12 ,  H10B53/20 ,  H10B12/00

CPC classification number: H01L29/78642 ,  H01L27/1203 ,  H01L27/13 ,  H10B12/05 ,  H10B12/31 ,  H10B53/20

Abstract: Some embodiments include an integrated transistor having an active region comprising semiconductor material. A conductive gating structure is adjacent to the active region. The conductive gating structure includes an inner region proximate the active region and includes an outer region distal from the active region. The inner region includes a first material containing titanium and nitrogen, and the outer region includes a metal-containing second material. The second material has a higher conductivity than the first material. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230255023A1

公开(公告)日：2023-08-10

申请号：US17665346

申请日：2022-02-04

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Richard J. Hill ,  Yoshiaki Fukuzumi ,  Paolo Tessariol

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565

CPC classification number: H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  G11C16/0483

Abstract: Memory circuitry comprising strings of memory cells comprising memory blocks individually comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers of the memory blocks extend from the memory-array region into a stair-step region. Individual of the memory blocks in the stair-step region comprise a flight of operative stairs. Individual of the operative stairs comprise one of the conductive tiers. At least some immediately-laterally-adjacent of the individual memory blocks in the stair-step region have their flights of operative stairs laterally-separated by a stack comprising two vertically-alternating different-composition insulative materials. Other embodiments, including method, are disclosed.