公开(公告)号：US20060092139A1

公开(公告)日：2006-05-04

申请号：US10978878

申请日：2004-11-01

Applicant: Manish Sharma

Inventor： Manish Sharma

IPC: G09G5/00

CPC classification number: G06F3/0412 ,  G06F3/045 ,  G06F2203/04104 ,  G06F2203/04809

Abstract: Provided is a pressure sensitive input device for data processing systems. In a particular embodiment, the device includes a transferable overlay for placement over a display screen of the system. Rows and columns of parallel conductors, which may be manufactured as ridges, are positioned to cross within the overlay, and are separated by a deformable isolation layer. A current is flowed across the rows and columns. Any change in the distance between the rows and columns, induced by the pressure of a user input, produces a disruption in the current flow. A proportional analog response signal is transmitted to a processor, wherein the signal is used to calculate a location of the user input, and a differential in the input pressure. The device may receive and process multiple, simultaneous inputs at various locations on the overlay. An appropriate method of use for the pressure-sensitive input device is also provided.

Abstract translation: 提供了一种用于数据处理系统的压敏输入装置。 在特定实施例中，设备包括用于放置在系统的显示屏幕上的可转移覆盖层。 可以制造为脊的平行导体的行和列被定位成在覆盖层内交叉，并且由可变形隔离层分开。 电流流过行和列。 由用户输入的压力引起的行和列之间的距离的任何变化导致当前流程的中断。 比例模拟响应信号被发送到处理器，其中该信号用于计算用户输入的位置和输入压力的差。 设备可以在覆盖层上的各个位置接收和处理多个同时输入。 还提供了适用于压敏输入装置的方法。

公开(公告)号：US20060072944A1

公开(公告)日：2006-04-06

申请号：US10958007

申请日：2004-10-04

Applicant: Manish Sharma ,  Lung Tran

Inventor： Manish Sharma ,  Lung Tran

IPC: G03G15/16

CPC classification number: H04L45/00 ,  G03G15/10 ,  G03G15/224 ,  G03G15/225 ,  G03G15/6585 ,  H04L45/24 ,  H04L45/245 ,  H04L45/60 ,  H05K3/1266 ,  H05K3/207 ,  H05K2201/0257 ,  H05K2203/0126 ,  H05K2203/0517 ,  Y02D50/30

Abstract: The invention provides a printed circuit board (PCB) printing system. In a particular embodiment, the system includes a liquid electrophotographic printing device. At least one supplier of electrically conductive ink supplying electrically conductive ink to the electrophotographic printing device is also provided. In addition, at least one supplier of dielectric ink supplying dielectric ink to the electrophotographic printing device is also provided. The liquid electrophotographic printing device is operable to apply the electrically conductive ink and the dielectric ink to a provided substrate such that substantially immiscible boundary delineation occurs at any points of contact between the applied electrically conducive ink and the applied dielectric ink. An appropriate method of use for the rendering of a printed circuit board is also provided.

公开(公告)号：US20060066338A1

公开(公告)日：2006-03-30

申请号：US11221394

申请日：2005-09-06

Applicant: Janusz Rajski ,  Gang Chen ,  Martin Keim ,  Nagesh Tamarapalli ,  Manish Sharma ,  Huaxing Tang

Inventor： Janusz Rajski ,  Gang Chen ,  Martin Keim ,  Nagesh Tamarapalli ,  Manish Sharma ,  Huaxing Tang

IPC: G01R31/26

CPC classification number: G06F11/2273 ,  G01R31/01 ,  G01R31/2846 ,  G01R31/2853 ,  G01R31/2894 ,  G01R31/31704 ,  G01R31/31835

Abstract: Methods, apparatus, and systems for testing, analyzing, and improving integrated circuit yield and quality are disclosed herein. For example, in one exemplary embodiment, one or more fault dictionaries are generated for identifying one or more defect candidates from corresponding observation point combinations. In this exemplary method, the observation point combinations indicate the observation points of a circuit-under-test that captured faulty test values upon application of a respective test pattern. Further, the one or more fault dictionaries in one embodiment are generated by: (a) for a first defect candidate, storing one or more first indicators indicative of test patterns detecting the first defect candidate, and (b) for a second defect candidate, storing at least a second indicator indicative of the test patterns that detect the second defect candidate, the second indicator comprising a bit mask that indicates which of the test patterns detecting the first defect candidate also detect the second defect candidate.

Abstract translation: 本文公开了用于测试，分析和提高集成电路产量和质量的方法，装置和系统。 例如，在一个示例性实施例中，生成用于从相应的观察点组合识别一个或多个缺陷候选的一个或多个故障字典。 在该示例性方法中，观察点组合表示在应用相应测试图案时捕获故障测试值的被测电路的观察点。 此外，一个实施例中的一个或多个故障字典通过以下方式产生：（a）对于第一缺陷候选，存储指示检测第一缺陷候选的测试图案的一个或多个第一指示符，以及（b）对于第二缺陷候选， 存储指示检测第二缺陷候选的测试图案的至少第二指示符，第二指示符包括指示检测第一缺陷候选的哪个测试图案还检测第二缺陷候选的位掩码。

公开(公告)号：US07009903B2

公开(公告)日：2006-03-07

申请号：US10855042

申请日：2004-05-27

Applicant: Fredrick A. Perner ,  Manish Sharma

Inventor： Fredrick A. Perner ,  Manish Sharma

IPC: G11C7/02

CPC classification number: G11C11/16

Abstract: A sense amplifying magnetic tunnel (SAMT) device is disclosed. In a particular embodiment, a field effect transistor (FET) having a drain, a source, a channel therebetween, a gate electrode and a tunneling gate oxide proximate to the channel is provided. In addition, a spin valve memory (SVM) cell is provided electrically coupled to the gate electrode. The electrical coupling between the SVM cell and the gate electrode serves to provide a control potential to the gate. In addition, the coupling provides a gain to a current passed through the SAMT device.

Abstract translation: 公开了一种感测放大磁通（SAMT）装置。 在特定实施例中，提供了具有漏极，源极，其间的沟道，靠近沟道的栅电极和隧道栅氧化物的场效应晶体管（FET）。 此外，提供电耦合到栅电极的自旋阀存储器（SVM）单元。 SVM单元和栅电极之间的电耦合用于向栅极提供控制电位。 此外，耦合为通过SAMT设备的电流提供增益。

公开(公告)号：US06989975B2

公开(公告)日：2006-01-24

申请号：US10463993

申请日：2003-06-18

Applicant: Janice H. Nickel ,  Manish Sharma

Inventor： Janice H. Nickel ,  Manish Sharma

IPC: G11B5/39

CPC classification number: B82Y25/00 ,  B82Y10/00 ,  G11B5/012 ,  G11B5/3903 ,  G11B5/3909 ,  G11B2005/3996 ,  G11C11/15 ,  H01F10/3254 ,  H01F10/3268 ,  H01F10/3295 ,  H01L43/08

Abstract: A magnetoresistive device includes a free ferromagnetic layer; a pinned structure; and a spacer layer between the free layer and the pinned structure. The pinned structure may include first, second and third ferromagnetic layers that are ferromagnetically coupled. The first and third layers are separated by the second layer. The second layer has a lower magnetic moment than the first and third layers. In the alternative, the pinned structure may include a single layer of Co50Fe50.

Abstract translation: 磁阻器件包括自由铁磁层; 固定结构 以及在自由层和钉扎结构之间的间隔层。 钉扎结构可以包括铁磁耦合的第一，第二和第三铁磁层。 第一和第三层由第二层隔开。 第二层具有比第一层和第三层更低的磁矩。 在替代方案中，钉扎结构可以包括单层Co 50 N 50 O 50。

公开(公告)号：US20050214953A1

公开(公告)日：2005-09-29

申请号：US10811553

申请日：2004-03-29

Applicant: Heon Lee ,  Thomas Anthony ,  Manish Sharma

Inventor： Heon Lee ,  Thomas Anthony ,  Manish Sharma

IPC: H01L21/8246 ,  H01L27/22 ,  H01L43/12 ,  H01L21/336

CPC classification number: H01L27/222 ,  H01L43/12

Abstract: A method of fabricating a magnetic random access memory (MRAM) device is disclosed. The method reduces the number of mask steps and processing steps required to fabricate the MRAM device. A first conductive layer and a sense layer are patterned in a first mask step. A subsequent etching step forms a bottom electrode and a sense layer that are continuous with each other in a first direction. A second conductive layer and a plurality of layers of material required to form a magnetic tunnel junction stack are patterned in a second mask step. A subsequent etching step forms a top electrode and a plurality of layers of material that are continuous with each other in a second direction, and a plurality of discrete sense layers. The discrete sense layers and the plurality of layers of material define a plurality of magnetic tunnel junction devices.

Abstract translation: 公开了制造磁随机存取存储器（MRAM）装置的方法。 该方法减少了制造MRAM设备所需的掩模步骤和处理步骤的数量。 第一导电层和感测层在第一掩模步骤中被图案化。 随后的蚀刻步骤形成在第一方向上彼此连续的底部电极和感测层。 在第二掩模步骤中图案化形成磁性隧道结叠层所需的第二导电层和多层材料。 随后的蚀刻步骤形成在第二方向上彼此连续的顶部电极和多个材料层，以及多个离散感测层。 离散感测层和多层材料限定了多个磁性隧道结装置。

公开(公告)号：US20050208769A1

公开(公告)日：2005-09-22

申请号：US10805471

申请日：2004-03-19

Applicant: Manish Sharma

Inventor： Manish Sharma

IPC: H01L21/306 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/336 ,  H01L27/22 ,  H01L21/20 ,  H01L21/302

CPC classification number: H01L21/32137 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/32134

Abstract: A semiconductor structure is fabricated by etching semiconductor material to form one or more recesses having side walls. The semiconductor material on the side walls is then reacted to form an oxide of the semiconductor material. This oxide may be then selectively removed from the side walls of the recess(es). This leads to a semiconductor structure having a high aspect ratio which is defined as the depth of the recess(es) divided by the width of the semiconductor material between the recess(es).

Abstract translation: 通过蚀刻半导体材料以形成具有侧壁的一个或多个凹槽来制造半导体结构。 然后使侧壁上的半导体材料反应以形成半导体材料的氧化物。 然后可以从凹部的侧壁选择性地去除该氧化物。 这导致具有高纵横比的半导体结构，其被定义为凹陷的深度除以凹部之间的半导体材料的宽度。

公开(公告)号：US20050201173A1

公开(公告)日：2005-09-15

申请号：US11089687

申请日：2005-03-24

Applicant: Manish Sharma ,  Lung Tran

Inventor： Manish Sharma ,  Lung Tran

IPC: G11C11/00 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  G11C7/00

CPC classification number: H01L27/224 ,  G11C11/00 ,  G11C11/15 ,  G11C11/16

Abstract: The method for manufacturing a data storage device is disclosed. The device has a plurality of word lines, a plurality of bit lines, and a resistive crosspoint array of memory cells. Each memory cell is connected to a bit line and connected to an isolation diode that further connects to a respective word line. The isolation diode provides a unidirectional conductive path from the bit line to the word line. Each word line provides a common metal-semiconductor contact with each diode sharing the word line such that each diode has a separate metal contact located between the semiconductor portion of the common metal-semiconductor contact and its respective memory cell.

Abstract translation: 公开了一种用于制造数据存储装置的方法。 该装置具有多个字线，多个位线和存储器单元的电阻交叉点阵列。 每个存储单元连接到位线并连接到进一步连接到相应字线的隔离二极管。 隔离二极管提供从位线到字线的单向导电路径。 每个字线提供与共享字线的每个二极管共同的金属 - 半导体接触，使得每个二极管具有位于公共金属 - 半导体触点的半导体部分和其相应存储单元之间的单独的金属触点。

公开(公告)号：US20050158881A1

公开(公告)日：2005-07-21

申请号：US10758659

申请日：2004-01-15

Applicant: Manish Sharma

Inventor： Manish Sharma

IPC: G11C11/16 ,  H01L21/00 ,  H01L21/336 ,  H01L43/12

CPC classification number: H01L43/12 ,  G11C11/16

Abstract: This invention provides a method of making nano-scaled toroidal magnetic memory cells, such as may be used, for example, in magnetic random access memory (MRAM). In a particular embodiment a semiconductor wafer substrate is prepared and a conductor layer is provided upon the wafer. A hard layer is deposited upon the first conductor. From the hard layer, ion etching is employed to form an annular wall about a pillar, the wall and pillar defining an annular slot. A ferromagnetic data layer is deposited within the annular slot and a junction stack is then provided upon at least a portion of the data layer. A dielectric is applied to insulate the structure and then planarized to expose the pillar.

Abstract translation: 本发明提供了一种制造纳米级环形磁存储器单元的方法，例如可用于例如磁性随机存取存储器（MRAM）。 在特定实施例中，制备半导体晶片衬底并且在晶片上提供导体层。 硬层沉积在第一导体上。 从硬层，使用离子蚀刻来形成围绕柱的环形壁，壁和柱限定环形槽。 铁磁数据层沉积在环形槽内，然后在数据层的至少一部分上提供结堆叠。 施加电介质以使结构绝缘，然后平坦化以暴露柱。

公开(公告)号：US20050157540A1

公开(公告)日：2005-07-21

申请号：US10758658

申请日：2004-01-15

Applicant: Fredrick Perner ,  Manish Sharma

Inventor： Fredrick Perner ,  Manish Sharma

IPC: H01L27/105 ,  G11C11/15 ,  H01L21/8246 ,  H01L43/08 ,  G11C11/00

CPC classification number: G11C11/15

Abstract: This invention provides a soft-reference four conductor magnetic memory storage device. In a particular embodiment, there are a plurality of parallel electrically conductive first sense conductors and a plurality of parallel electrically conductive second sense conductors. The first and second sense conductors may provide a cross point array or a series connected array. Soft-reference magnetic memory cells are provided in electrical contact with and located and at each intersection. In addition there are a plurality of parallel electrically conductive write rows substantially proximate to and electrically isolated from the first sense conductors. A plurality of parallel electrically conductive write columns transverse to the write rows, substantially proximate to and electrically isolated from the second sense conductors, forming a write cross point array with a plurality of intersections, is also provided. Sense magnetic fields generated by at least one conductor orient the soft-reference layer but do not alter the data stored within the cell. An associated method of use is also provided.

Abstract translation: 本发明提供一种软参考四导体磁存储器存储装置。 在特定实施例中，存在多个平行导电的第一感测导体和多个平行导电的第二感测导体。 第一和第二感测导体可以提供交叉点阵列或串联连接的阵列。 软参考磁存储器单元与每个交叉点电接触并定位和设置。 此外，还存在多个平行的导电写入行，其基本上接近并与第一感测导体电隔离。 还提供了横向于写入行的多个平行的导电写入列，其基本上接近第二感测导体并与第二感测导体电隔离，形成具有多个交点的写入交叉点阵列。 由至少一个导体产生的感测磁场定向软参考层，但不改变存储在单元内的数据。 还提供了相关联的使用方法。