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公开(公告)号：US07351626B2
公开(公告)日：2008-04-01
申请号：US10739617
申请日：2003-12-18
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/02318 , C23C16/56 , H01L21/02323 , H01L21/28185 , H01L21/28194 , H01L21/3143 , H01L21/31608 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/318 , H01L29/518 , H01L29/78
摘要： A method for improving high-κ gate dielectric film (104) properties. The high-κ film (104) is subjected to a two step anneal sequence. The first anneal is performed in a reducing ambient (106) with low partial pressure of oxidizer to promote film relaxation and increase by-product diffusion and desorption. The second anneal is performed in an oxidizing ambient (108) with a low partial pressure of reducer to remove defects and impurities.
摘要翻译： 一种改善高卡门电介质膜（104）性能的方法。 对高卡帕膜（104）进行两步退火处理。 第一退火在具有低分压氧化剂的还原环境（106）中进行，以促进膜弛豫并增加副产物扩散和解吸附。 第二次退火在具有低分压还原剂的氧化环境（108）中进行以除去缺陷和杂质。
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公开(公告)号：US07015088B2
公开(公告)日：2006-03-21
申请号：US10335560
申请日：2002-12-31
IPC分类号： H01L21/00 , H01L21/8242
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/517 , H01L29/518 , H01L29/6659
摘要： One or more aspects of the present invention relate to forming a transistor while passivating electrically active defects associated with a top portion of a layer of high-k dielectric material. The layer of high-k dielectric material is utilized to establish a high-k gate dielectric in the transistor. A gate electrode layer is formed over the layer of high-k dielectric material, and is patterned to form a gate structure that includes a gate electrode and the high-k gate dielectric. The electrically active defects are passivated utilizing materials containing dopants that are attracted to and neutralize the defects. The passivated defects thus do not interfere with other transistor doping processes (e.g., forming source and drain regions) and do not adversely affect resulting semiconductor device performance, reliability and yield.
摘要翻译： 本发明的一个或多个方面涉及形成晶体管，同时钝化与高k电介质材料层的顶部相关联的电活性缺陷。 高k介电材料层用于在晶体管中建立高k栅极电介质。 栅电极层形成在高k电介质材料层上，并被图案化以形成包括栅电极和高k栅电介质的栅结构。 使用含有被吸引并中和缺陷的掺杂剂的材料来钝化电活性缺陷。 钝化的缺陷因此不干扰其它晶体管掺杂过程（例如，形成源极和漏极区），并且不会对所得到的半导体器件性能，可靠性和产量产生不利影响。
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63.发明授权Method for fabricating split gate transistor device having high-k dielectrics 有权具有高k电介质的分离栅晶体管器件的制造方法公开(公告)号：US06979623B2
公开(公告)日：2005-12-27
申请号：US10738957
申请日：2003-12-17
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/4763 , H01L29/51
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/518
摘要： Methods and systems are disclosed that facilitate semiconductor fabrication by fabricating transistor devices having gate dielectrics with selectable thicknesses in different regions of semiconductor devices. The thicknesses correspond to operating voltages of the corresponding transistor devices. Furthermore, the present invention also provides systems and methods that can fabricate the gate dielectrics with high-k dielectric material, which allows a thicker gate dielectric than conventional silicon dioxide.
摘要翻译： 公开了通过制造具有在半导体器件的不同区域中具有可选厚度的栅极电介质的晶体管器件来促进半导体制造的方法和系统。 厚度对应于相应的晶体管器件的工作电压。 此外，本发明还提供了可以制造具有高k电介质材料的栅极电介质的系统和方法，其允许比常规二氧化硅更厚的栅极电介质。
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64.发明授权High-k gate dielectric with uniform nitrogen profile and methods for making the same 有权具有均匀氮分布的高k栅极电介质及其制造方法公开(公告)号：US06809370B1
公开(公告)日：2004-10-26
申请号：US10632230
申请日：2003-07-31
申请人： Luigi Colombo , Manuel Quevedo-Lopez , James J. Chambers , Mark R. Visokay , Antonio L. P. Rotondaro
发明人： Luigi Colombo , Manuel Quevedo-Lopez , James J. Chambers , Mark R. Visokay , Antonio L. P. Rotondaro
IPC分类号： H01L27108
CPC分类号： H01L29/518 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/6659 , H01L29/7833
摘要： High-k transistor gate structures and fabrication methods therefor are provided, wherein a gate dielectric interface region near a semiconductor substrate is provided with very little or no nitrogen, while the bulk high-k dielectric is provided with a uniform nitrogen concentration.
摘要翻译： 提供了高k晶体管栅极结构及其制造方法，其中在半导体衬底附近的栅极电介质界面区域设置有非常少的或不具有氮的，而本体高k电介质具有均匀的氮浓度。
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65.发明授权Bilayer deposition to avoid unwanted interfacial reactions during high K gate dielectric processing 有权双层沉积以避免在高K栅介质处理期间的不希望的界面反应公开(公告)号：US06696332B2
公开(公告)日：2004-02-24
申请号：US10176596
申请日：2002-06-21
IPC分类号： H01L218238
CPC分类号： H01L21/28185 , H01L21/2652 , H01L21/28194 , H01L21/28202 , H01L21/28238 , H01L21/28291 , H01L29/513 , H01L29/517 , H01L29/518
摘要： Methods are disclosed for forming gate dielectrics for MOSFET transistors, wherein a bilayer deposition of a nitride layer and an oxide layer are used to form a gate dielectric stack. The nitride layer is formed on the substrate to prevent oxidation of the substrate material during deposition of the oxide layer, thereby avoiding or mitigating formation of low-k interfacial layer.
摘要翻译： 公开了用于形成用于MOSFET晶体管的栅极电介质的方法，其中使用氮化物层和氧化物层的双层沉积来形成栅极电介质叠层。 在衬底上形成氮化物层以防止氧化物层沉积期间衬底材料的氧化，从而避免或减轻低k界面层的形成。
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公开(公告)号：US06528386B1
公开(公告)日：2003-03-04
申请号：US10097919
申请日：2002-03-13
申请人： Scott R. Summerfelt , Luigi Colombo , Stephen R. Gilbert , Theodore S. Moise, IV , Sanjeev Aggarwal
发明人： Scott R. Summerfelt , Luigi Colombo , Stephen R. Gilbert , Theodore S. Moise, IV , Sanjeev Aggarwal
IPC分类号： H01L2176
CPC分类号： H01L27/11502 , H01L27/11507
摘要： A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the patterning of a top electrode layer and a dielectric layer to form a capacitor stack structure having sidewalls associated therewith. Prior to patterning the bottom electrode layer, a protective film is formed on the sidewalls of the capacitor stack structure in order to protect the dielectric material from conductive contaminants associated with a subsequent patterning of the bottom electrode layer.
摘要翻译： 公开了一种制造铁电电容器的方法。 该方法包括图案化顶部电极层和电介质层以形成具有与其相关联的侧壁的电容器堆叠结构。 在图形化底部电极层之前，在电容器堆叠结构的侧壁上形成保护膜，以保护电介质材料免受与随后的底部电极层的图案化有关的导电污染物的影响。
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公开(公告)号：US20130019399A1
公开(公告)日：2013-01-24
申请号：US13637778
申请日：2011-04-11
申请人： Luigi Colombo
发明人： Luigi Colombo
CPC分类号： A47C17/40
摘要： A pull-down bed assembly including a movable frame which constitutes the bedspring and is pivoted to a fixed frame so as to define a closed vertical position, in which the movable frame is substantially in a vertical position, and an open horizontal position, for use as a bed, in which the movable frame is in the horizontal position; the assembly has a balancing system, which is adapted to control the movement of the movable frame with respect to the fixed frame. The balancing system is constituted by springs with a respective transmission mechanism, which are arranged within the fixed frame and the movable frame and are not visible from the outside both in the closed position and in the open position of the movable frame.
摘要翻译： 一种下拉床组件，其包括构成床垫的可移动框架，并且枢转到固定框架，以便限定可闭合的框架基本处于垂直位置的闭合的垂直位置和用于使用的开放的水平位置 作为可移动框架处于水平位置的床; 组件具有平衡系统，其适于控制可移动框架相对于固定框架的移动。 平衡系统由具有各自的传动机构的弹簧构成，其布置在固定框架和可移动框架内，并且在关闭位置和可移动框架的打开位置都不能从外部看到。
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68.发明授权公开(公告)号：US08309438B2
公开(公告)日：2012-11-13
申请号：US12706116
申请日：2010-02-16
IPC分类号： H01L21/20
CPC分类号： H01L21/02612 , H01L21/02527
摘要： A method and semiconductor device for synthesizing graphene using ion implantation of carbon. Carbon is implanted in a metal using ion implantation. After the carbon is distributed in the metal, the metal is annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the surface of the metal. The metal/graphene surface is then transferred to a dielectric layer in such a manner that the graphene layer is placed on top of the dielectric layer. The metal layer is then removed. Alternatively, recessed regions are patterned and etched in a dielectric layer located on a substrate. Metal is later formed in these recessed regions. Carbon is then implanted into the metal using ion implantation. The metal may then be annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the metal's surface.
摘要翻译： 一种使用碳的离子注入合成石墨烯的方法和半导体器件。 使用离子注入将碳注入金属中。 在碳分布在金属中之后，对金属进行退火和冷却，以便从金属沉淀碳以在金属表面上形成一层石墨烯。 然后将金属/石墨烯表面转移到电介质层，使得石墨烯层被放置在电介质层的顶部上。 然后去除金属层。 或者，凹陷区域被图案化并蚀刻在位于基底上的电介质层中。 金属后来形成在这些凹陷区域。 然后使用离子注入将碳注入到金属中。 然后可以对金属进行退火和冷却，以便从金属沉淀碳以在金属表面上形成一层石墨烯。
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69.发明申请公开(公告)号：US20120164820A1
公开(公告)日：2012-06-28
申请号：US13404840
申请日：2012-02-24
CPC分类号： H01L21/28079 , H01L21/02068 , H01L21/3003 , H01L21/321 , H01L21/823842
摘要： The invention provides a method for manufacturing a semiconductor device that comprises placing a metallic gate layer over a gate dielectric layer where the metallic gate layer has a crystallographic orientation, and re-orienting the crystallographic orientation of the metallic gate layer by subjecting the metallic gate layer to a hydrogen anneal.
摘要翻译： 本发明提供了一种制造半导体器件的方法，该方法包括将金属栅极层放置在栅极电介质层上，其中金属栅极层具有晶体取向，并通过对金属栅极层进行金属栅极层的重新取向来取向晶体取向 进行氢退火。
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70.发明授权公开(公告)号：US08124529B2
公开(公告)日：2012-02-28
申请号：US11421671
申请日：2006-06-01
IPC分类号： H01L21/44
CPC分类号： H01L21/28079 , H01L21/02068 , H01L21/3003 , H01L21/321 , H01L21/823842
摘要： The invention provides a method for manufacturing a semiconductor device that comprises placing a metallic gate layer over a gate dielectric layer where the metallic gate layer has a crystallographic orientation, and re-orienting the crystallographic orientation of the metallic gate layer by subjecting the metallic gate layer to a hydrogen anneal.
摘要翻译： 本发明提供了一种制造半导体器件的方法，该方法包括将金属栅极层放置在栅极电介质层上，其中金属栅极层具有晶体取向，并通过对金属栅极层进行金属栅极层的重新取向来取向晶体取向 进行氢退火。
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