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    SIGNAL CONVERSION USING FINITE IMPULSE RESPONSE FEEDBACK
    61.
    发明申请
    SIGNAL CONVERSION USING FINITE IMPULSE RESPONSE FEEDBACK 有权
    信号转换使用有限的反应反馈

    公开(公告)号：US20100045500A1

    公开(公告)日：2010-02-25

    申请号：US12610176

    申请日：2009-10-30

    申请人： Luis Hernandez ,  Dietmar Straussnigg ,  Andreas Wiesbauer

    发明人： Luis Hernandez ,  Dietmar Straussnigg ,  Andreas Wiesbauer

    IPC分类号： H03M3/00 ,  H03M1/12

    CPC分类号： H03M3/344 ,  H03M1/504 ,  H03M3/372 ,  H03M3/46

    摘要： Disclosed are techniques for reducing noise and providing conversion signals in electronic components, including pulse width modulation (PWM) oversampling converters, by performing signal conversion having finite impulse response (FIR) feedback. Implementations may reduce the sensitivity of the conversion process to jitter in the sampling clock, thereby reducing noise and providing conversion signals.

    摘要翻译： 公开了通过执行具有有限脉冲响应（FIR）反馈的信号转换来减少噪声和提供电子部件中的转换信号的技术，包括脉宽调制（PWM）过采样转换器。 实现可能会降低采样时钟中转换过程对抖动的灵敏度，从而降低噪声并提供转换信号。

    AMPLIFIER MODULATION METHOD AND APPARATUS
    64.
    发明申请
    AMPLIFIER MODULATION METHOD AND APPARATUS 有权
    放大器调制方法和装置

    公开(公告)号：US20090184761A1

    公开(公告)日：2009-07-23

    申请号：US12017218

    申请日：2008-01-21

    申请人： Patrick Reynaert ,  Andreas Wiesbauer ,  Thomas Potscher ,  Koen Mertens

    发明人： Patrick Reynaert ,  Andreas Wiesbauer ,  Thomas Potscher ,  Koen Mertens

    IPC分类号： H03F3/38 ,  H03C1/52

    CPC分类号： H04B1/0458 ,  H03F1/56 ,  H03F3/2171 ,  H03F3/245 ,  H04B1/0475

    摘要： One embodiment relates to a power amplifier that includes a switched mode power amplification stage. The power amplification stage has an output configured to provide an amplified output voltage as a function of a drive signal, where the drive signal fluctuates during a first time and is inactive during a second time. The power amplifier also includes impedance compensation circuitry coupled to the output of the power amplification stage. The impedance compensation circuitry can selectively alter an output impedance of the power amplification stage as a function of a control signal that is continuously de-asserted during the first time and continuously asserted during the second time. Other embodiments are also disclosed.

    摘要翻译： 一个实施例涉及包括开关模式功率放大级的功率放大器。 功率放大级具有被配置为提供作为驱动信号的函数的放大输出电压的输出，其中驱动信号在第一时间期间波动并且在第二时间期间不活动。 功率放大器还包括耦合到功率放大级的输出的阻抗补偿电路。 阻抗补偿电路可以根据控制信号选择性地改变功率放大级的输出阻抗，该控制信号在第一时间期间连续地被断言并且在第二时间期间连续断言。 还公开了其他实施例。

    Sigma-Delta Analog-Digital Converter For An Xdsl Multistandard Input Stage
    67.
    发明申请
    Sigma-Delta Analog-Digital Converter For An Xdsl Multistandard Input Stage 失效
    用于Xdsl多标准输入级的Sigma-Delta模拟数字转换器

    公开(公告)号：US20080297385A1

    公开(公告)日：2008-12-04

    申请号：US11661627

    申请日：2004-09-02

    申请人： Martin Clara ,  Antonio Di Giandomenico ,  Joerg Hauptmann ,  Andreas Wiesbauer

    发明人： Martin Clara ,  Antonio Di Giandomenico ,  Joerg Hauptmann ,  Andreas Wiesbauer

    IPC分类号： H03M3/04

    CPC分类号： H03M3/394 ,  H03M3/406 ,  H03M3/424 ,  H03M3/452

    摘要： The invention relates to a sigma-delta analogue/digital converter for an xDSL multi-standard input stage for converting an xDSL signal into a digital output signal, where the sigma-delta analogue/digital converter (1) has: an analogue loop filter (6) which filters an analogue difference signal between the xDSL signal to be converted and a feedback signal in order to produce a filter output signal; a quantizer which quantizes the filter output signal from the analogue loop filter (6) in order to produce the digital output signal; a first digital/analogue converter (16) which converts the digital output signal into the analogue feedback signal; where the analogue loop filter (6) has at least two resonator filter stages (6a, 6b) which respectively comprise a first integrator (6a-1; 6b-1) and a second integrator (6a-2; 6b-2) connected in series therewith, where the second integrator (6a-2; 6b-2) can be connected to the first integrator (6a-1, 6b-1) by means of a controllable feedback switch (6a-3, 6b-3) in order to close a local feedback loop, where the integrator outputs can respectively be connected by means of a controllable switch (25) to a signal input of an adder (27) which adds the output signals from the integrators in order to produce the filter output signal.

    摘要翻译： 本发明涉及一种用于xDSL多标准输入级的Σ-Δ模拟/数字转换器，用于将xDSL信号转换成数字输出信号，其中Σ-Δ模拟/数字转换器（1）具有：模拟环路滤波器 6），其对要转换的xDSL信号和反馈信号之间的模拟差分信号进行滤波，以产生滤波器输出信号; 量化器，其量化来自模拟环路滤波器（6）的滤波器输出信号，以产生数字输出信号; 第一数字/模拟转换器（16），其将数字输出信号转换成模拟反馈信号; 其中模拟环路滤波器（6）具有至少两个分别包括第一积分器（6a-1; 6b-1）和第二积分器（6a-2; 6b-2）的谐振器滤波器级（6a，6b） 其中第二积分器（6a-2; 6b-2）可以通过可控反馈开关（6a-3,6b-3）按顺序连接到第一积分器（6a-1,6b-1） 以闭合局部反馈回路，其中积分器输出可以分别通过可控开关（25）连接到加法器（27）的信号输入端，加法器（27）的信号输入相加来自积分器的输出信号，以产生滤波器输出信号 。

    Compensation circuit for clock jitter compensation
    69.
    发明授权
    Compensation circuit for clock jitter compensation 有权
    时钟抖动补偿补偿电路

    公开(公告)号：US07262723B2

    公开(公告)日：2007-08-28

    申请号：US11451229

    申请日：2006-06-12

    申请人： Dietmar Straussnig ,  Bernd Rainer ,  Andreas Wiesbauer ,  Richard Gaggl ,  Martin Clara ,  Luis Hernandez

    发明人： Dietmar Straussnig ,  Bernd Rainer ,  Andreas Wiesbauer ,  Richard Gaggl ,  Martin Clara ,  Luis Hernandez

    IPC分类号： H03M1/10

    CPC分类号： H03M1/0836 ,  H03M1/66

    摘要： A compensation circuit for a digital/analogue converter, which is clocked by a clock signal comprising a jitter and converts a digital input data signal into an analogue output data signal comprising a jitter error due to said jitter, comprises a measurement circuit for measuring the jitter and a modelling circuit for generating a digital modelled jitter error signal which simulates the jitter error dependent on the measured jitter and the digital input data signal, wherein the digital modelled jitter error signal is subtracted from the digital input data signal.

    摘要翻译： 一种用于数/模转换器的补偿电路，其由包括抖动的时钟信号计时，并将数字输入数据信号转换成包括由于所述抖动引起的抖动误差的模拟输出数据信号，包括用于测量抖动的测量电路 以及用于产生数字建模的抖动误差信号的建模电路，其根据所测量的抖动和数字输入数据信号模拟抖动误差，其中从数字输入数据信号中减去数字建模的抖动误差信号。