公开(公告)号：US20120261728A1

公开(公告)日：2012-10-18

申请号：US13529558

申请日：2012-06-21

申请人： Dechao Guo ,  Shu-Jen Han ,  Pranita Kulkarni ,  Philip J. Oldiges

发明人： Dechao Guo ,  Shu-Jen Han ,  Pranita Kulkarni ,  Philip J. Oldiges

IPC分类号： H01L29/78

CPC分类号： H01L29/1054 ,  H01L29/517 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78687

摘要： A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a plurality of spacers disposed on laterally opposing sides of the gate stack; source and drain regions proximate to the spacers, and a channel region subjacent to the gate stack and disposed between the source and drain regions; and a stressor subjacent to the channel region, and embedded within the semiconductor substrate, the embedded stressor being formed of a triangular-shape.

摘要翻译： 半导体结构包括半导体衬底; 半导体衬底上的栅极堆叠; 设置在所述栅极堆叠的横向相对侧上的多个间隔件; 邻近间隔物的源极和漏极区域以及位于栅极堆叠下方并设置在源极和漏极区域之间的沟道区域; 以及位于所述沟道区域的下方并嵌入在所述半导体衬底内的应力器，所述嵌入式应力器由三角形形成。

公开(公告)号：US20120187505A1

公开(公告)日：2012-07-26

申请号：US13013206

申请日：2011-01-25

申请人： Dechao Guo ,  Shu-Jen Han ,  Jeehwan Kim ,  Kuen-Ting Shiu

发明人： Dechao Guo ,  Shu-Jen Han ,  Jeehwan Kim ,  Kuen-Ting Shiu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/8252 ,  H01L21/26546 ,  H01L21/28575 ,  H01L21/3245 ,  H01L29/0847 ,  H01L29/201 ,  H01L29/207 ,  H01L29/41783 ,  H01L29/452 ,  H01L29/66446 ,  H01L29/66477 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/78

摘要： A method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing raised source/drain regions on the source/drain regions, the grown raised source/drain regions including III-V semiconductor material, and growing metal contacts on the grown raised source/drain regions. Another method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing metal contacts on the source/drain regions. Transistors and computer program products are also disclosed.

摘要翻译： 一种用于形成晶体管的方法，包括提供设置在III-V衬底上并且具有形成在图案化栅极堆叠的侧面上的侧壁间隔物的图案化栅极堆叠，所述III-V衬底包括与侧壁间隔物相邻的源极/漏极区域和场氧化物 与源/漏区相邻形成的区域。 该方法包括在源极/漏极区域上生长凸起的源极/漏极区域，生长的升高的源极/漏极区域包括III-V半导体材料，以及在生长的升高的源极/漏极区域上生长的金属接触。 形成晶体管的另一种方法包括提供设置在III-V衬底上并且具有形成在图案化栅极堆叠的侧面上的侧壁间隔物的图案化栅极堆叠，所述III-V衬底包括与侧壁间隔物相邻的源极/漏极区域和场氧化物 与源/漏区相邻形成的区域。 该方法包括在源/漏区上生长金属接触。 还公开了晶体管和计算机程序产品。

公开(公告)号：US20120112310A1

公开(公告)日：2012-05-10

申请号：US13351041

申请日：2012-01-16

申请人： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

发明人： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

IPC分类号： H01L29/06

CPC分类号： H01L21/76224 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

摘要： A method of forming diffusion sidewalls in a semiconductor structure and a semiconductor structure having diffusion sidewalls includes etching a trench into a semiconductor substrate to form first and second active regions, lining each trench with an oxide liner along exposed sidewalls of an active silicon region (RX) of the first and second active regions, removing the oxide liner formed along the exposed sidewalls of the RX region of one of the first and second active regions, forming diffusion sidewalls by epitaxially growing in-situ doped material within the exposed sidewalls of the RX region of the one of the first and second active regions, and forming an isolation region within the trench between the first and second active regions to electrically isolate the first and second active regions from each other.

摘要翻译： 在半导体结构中形成扩散侧壁的方法和具有扩散侧壁的半导体结构的方法包括将沟槽蚀刻到半导体衬底中以形成第一和第二有源区，沿着有源硅区（RX ）去除沿着第一和第二有源区域之一的RX区域的暴露的侧壁形成的氧化物衬垫，通过在RX的暴露侧壁内外延生长原位掺杂材料来形成扩散侧壁 区域，并且在第一和第二有源区域之间的沟槽内形成隔离区域，以将第一和第二有源区域彼此电隔离。

公开(公告)号：US20120007181A1

公开(公告)日：2012-01-12

申请号：US12834428

申请日：2010-07-12

申请人： Jin Cai ,  Dechao Guo ,  Marwan H. Khater ,  Christian Lavoie ,  Zhen Zhang

发明人： Jin Cai ,  Dechao Guo ,  Marwan H. Khater ,  Christian Lavoie ,  Zhen Zhang

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L29/66772 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66621

摘要： A method for forming a field effect transistor (FET) includes forming a dummy gate on a top semiconductor layer of a semiconductor on insulator substrate; forming source and drain regions in the top semiconductor layer, wherein the source and drain regions are located in the top semiconductor layer on either side of the dummy gate; forming a supporting material over the source and drain regions adjacent to the dummy gate; removing the dummy gate to form a gate opening, wherein a channel region of the top semiconductor layer is exposed through the gate opening; thinning the channel region of the top semiconductor layer through the gate opening; and forming gate spacers and a gate in the gate opening over the thinned channel region.

摘要翻译： 一种形成场效应晶体管（FET）的方法包括在绝缘体上半导体衬底的顶部半导体层上形成一个虚拟栅极; 在顶部半导体层中形成源极和漏极区域，其中源极和漏极区域位于虚拟栅极的任一侧的顶部半导体层中; 在与所述虚拟栅极相邻的所述源极和漏极区域上形成支撑材料; 去除所述伪栅极以形成栅极开口，其中所述顶部半导体层的沟道区域通过所述栅极开口暴露; 通过栅极开口来稀薄顶部半导体层的沟道区域; 以及在所述变薄的通道区域上的所述栅极开口中形成栅极间隔物和栅极。

公开(公告)号：US20110316565A1

公开(公告)日：2011-12-29

申请号：US12825527

申请日：2010-06-29

申请人： Dechao Guo ,  Christian Lavoie ,  Christine Qiqing Ouyang ,  Yanning Sun ,  Zhen Zhang

发明人： Dechao Guo ,  Christian Lavoie ,  Christine Qiqing Ouyang ,  Yanning Sun ,  Zhen Zhang

IPC分类号： G01R27/26 ,  H01L21/338 ,  H01L29/772 ,  H01L29/775

CPC分类号： G01N27/4145 ,  G01N27/4146 ,  H01L29/0673

摘要： A Schottky junction silicon nanowire field-effect biosensor/molecule detector with a nanowire thickness of 10 nanometer or less and an aligned source/drain workfunction for increased sensitivity. The nanowire channel is coated with a surface treatment to which a molecule of interest absorbs, which modulates the conductivity of the channel between the Schottky junctions sufficiently to qualitatively and quantitatively measure the presence and amount of the molecule.

摘要翻译： 肖特基结的硅纳米线场效应生物传感器/分子检测器，纳米线厚度为10纳米或更小，并具有对准的源极/漏极功能，以提高灵敏度。 纳米线通道涂覆有目标分子吸收的表面处理，其可以充分调节肖特基结之间的通道的电导率以定性和定量地测量分子的存在和量。

公开(公告)号：US20110315961A1

公开(公告)日：2011-12-29

申请号：US12826221

申请日：2010-06-29

申请人： Zhihong Chen ,  Dechao Guo ,  Shu-Jen Han ,  Kai Zhao

发明人： Zhihong Chen ,  Dechao Guo ,  Shu-Jen Han ,  Kai Zhao

IPC分类号： H01L29/76 ,  H01L29/78 ,  H01L21/334

CPC分类号： H01L29/1606 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/7781 ,  H01L29/78684

摘要： A method for formation of a carbon-based field effect transistor (FET) includes depositing a first dielectric layer on a carbon layer located on a substrate; forming a gate electrode on the first dielectric layer; etching an exposed portion of the first dielectric layer to expose a portion of the carbon layer; depositing a second dielectric layer over the gate electrode to form a spacer, wherein the second dielectric layer is deposited by atomic layer deposition (ALD), and wherein the second dielectric layer does not form on the exposed portion of the carbon layer; forming source and drain contacts on the carbon layer and forming a gate contact on the gate electrode to form the carbon-based FET.

摘要翻译： 一种用于形成碳基场效应晶体管（FET）的方法包括：在位于衬底上的碳层上沉积第一介电层; 在所述第一电介质层上形成栅电极; 蚀刻第一介电层的暴露部分以暴露碳层的一部分; 在所述栅电极上沉积第二电介质层以形成间隔物，其中所述第二电介质层通过原子层沉积（ALD）沉积，并且其中所述第二电介质层不在所述碳层的暴露部分上形成; 在碳层上形成源极和漏极接触，并在栅电极上形成栅极接触以形成碳基FET。

公开(公告)号：US20110248343A1

公开(公告)日：2011-10-13

申请号：US12755720

申请日：2010-04-07

申请人： Dechao Guo ,  Marwan Khater ,  Christian Lavoie ,  Qiqing Ouyang ,  Zhen Zhang

发明人： Dechao Guo ,  Marwan Khater ,  Christian Lavoie ,  Qiqing Ouyang ,  Zhen Zhang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/26513 ,  H01L21/265 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/66643 ,  H01L29/7839

摘要： A method for forming a Schottky field effect transistor (FET) includes forming a gate stack on a silicon substrate, the gate stack comprising a gate polysilicon on top of a gate metal layer; depositing a metal layer over the gate polysilicon and the silicon substrate; annealing the metal layer, the gate polysilicon, and the silicon substrate such that the metal layer fully consumes the gate polysilicon to form a gate silicide and reacts with portions of the silicon substrate to form source/drain silicide regions in the silicon substrate; and in the event a portion of the metal layer does not react with the gate polysilicon or the silicon substrate, removing the unreacted portion of the metal layer.

摘要翻译： 一种用于形成肖特基场效应晶体管（FET）的方法包括在硅衬底上形成栅极堆叠，所述栅叠层在栅极金属层的顶部包括栅极多晶硅; 在栅极多晶硅和硅衬底上沉积金属层; 使金属层，栅极多晶硅和硅衬底退火，使得金属层完全消耗栅极多晶硅以形成栅极硅化物，并与硅衬底的部分反应以在硅衬底中形成源极/漏极硅化物区域; 并且在金属层的一部分不与栅极多晶硅或硅衬底反应的情况下，去除金属层的未反应部分。

公开(公告)号：US20110248321A1

公开(公告)日：2011-10-13

申请号：US12757201

申请日：2010-04-09

申请人： Dechao Guo ,  Wilfried E. Haensch ,  Xinhui Wang ,  Keith Kwong Hon Wong

发明人： Dechao Guo ,  Wilfried E. Haensch ,  Xinhui Wang ,  Keith Kwong Hon Wong

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/665 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28525 ,  H01L21/76897 ,  H01L21/78 ,  H01L29/66545

摘要： A method for forming a field effect transistor includes forming a gate stack, a spacer adjacent to opposing sides of the gate stack, a silicide source region and a silicide drain region on opposing sides of the spacer, epitaxially growing silicon on the source region and the drain region; forming a liner layer on the gate stack and the spacer, removing a portion of the liner layer to expose a portion of the hardmask layer, removing the exposed portions of the hardmask layer to expose a silicon layer of the gate stack, removing exposed silicon to expose a portion of a metal layer of the gate stack, the source region, and the drain region; and depositing a conductive material on the metal layer of the gate stack, the silicide source region, and the silicide drain region.

摘要翻译： 一种用于形成场效应晶体管的方法，包括：形成栅极叠层，与栅叠层的相对侧相邻的间隔物，在间隔物的相对侧上的硅化物源区和硅化物漏极区，在源区上外延生长硅， 漏区; 在栅极堆叠和间隔物上形成衬垫层，去除衬里层的一部分以露出硬掩模层的一部分，去除硬掩模层的暴露部分以暴露栅堆叠的硅层，将暴露的硅去除 暴露栅叠层，源极区和漏区的金属层的一部分; 以及在栅叠层，硅化物源区和硅化物漏极区的金属层上沉积导电材料。

公开(公告)号：US20110115044A1

公开(公告)日：2011-05-19

申请号：US12621216

申请日：2009-11-18

申请人： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

发明人： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

摘要： A method of forming diffusion sidewalls in a semiconductor structure and a semiconductor structure having diffusion sidewalls includes etching a trench into a semiconductor substrate to form first and second active regions, lining each trench with an oxide liner along exposed sidewalls of an active silicon region (RX) of the first and second active regions, removing the oxide liner formed along the exposed sidewalls of the RX region of one of the first and second active regions, forming diffusion sidewalls by epitaxially growing in-situ doped material within the exposed sidewalls of the RX region of the one of the first and second active regions, and forming an isolation region within the trench between the first and second active regions to electrically isolate the first and second active regions from each other.

摘要翻译： 在半导体结构中形成扩散侧壁的方法和具有扩散侧壁的半导体结构的方法包括将沟槽蚀刻到半导体衬底中以形成第一和第二有源区，沿着有源硅区（RX ）去除沿着第一和第二有源区域之一的RX区域的暴露的侧壁形成的氧化物衬垫，通过在RX的暴露侧壁内外延生长原位掺杂材料来形成扩散侧壁 区域，并且在第一和第二有源区域之间的沟槽内形成隔离区域，以将第一和第二有源区域彼此电隔离。

公开(公告)号：US20110095379A1

公开(公告)日：2011-04-28

申请号：US12607110

申请日：2009-10-28

申请人： Keith Kwong Hon Wong ,  Dechao Guo ,  Unoh Kwon

发明人： Keith Kwong Hon Wong ,  Dechao Guo ,  Unoh Kwon

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/511 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545

摘要： A method of forming a p-type semiconductor device is provided, which in one embodiment employs an aluminum containing threshold voltage shift layer to produce a threshold voltage shift towards the valence band of the p-type semiconductor device. The method of forming the p-type semiconductor device may include forming a gate structure on a substrate, in which the gate structure includes a gate dielectric layer in contact with the substrate, an aluminum containing threshold voltage shift layer present on the gate dielectric layer, and a metal containing layer in contact with at least one of the aluminum containing threshold voltage shift layer and the gate dielectric layer. P-type source and drain regions may be formed in the substrate adjacent to the portion of the substrate on which the gate structure is present. A p-type semiconductor device provided by the above-described method is also provided.

摘要翻译： 提供一种形成p型半导体器件的方法，其在一个实施例中使用含铝的阈值电压移位层，以产生朝向p型半导体器件的价带的阈值电压偏移。 形成p型半导体器件的方法可以包括在衬底上形成栅极结构，其中栅极结构包括与衬底接触的栅极电介质层，存在于栅极电介质层上的含铝的阈值电压移位层， 以及与含铝的阈值电压移位层和栅极电介质层中的至少一个接触的含金属层。 P型源极和漏极区可以形成在衬底附近，栅极结构所在的衬底的相邻部分。 还提供了通过上述方法提供的p型半导体器件。