公开(公告)号：US6018405A

公开(公告)日：2000-01-25

申请号：US244856

申请日：1999-02-05

申请人： Keiji Tomooka ,  Naohiro Sakakida ,  Shin Nishimura ,  Yoshihiro Ashi ,  Hironari Matsuda ,  Satoshi Aoki ,  Yukio Nakano ,  Masahiro Takatori ,  Toru Kazawa ,  Shinya Sasaki ,  Ryoji Takeyari ,  Hiroyuki Nakano

发明人： Keiji Tomooka ,  Naohiro Sakakida ,  Shin Nishimura ,  Yoshihiro Ashi ,  Hironari Matsuda ,  Satoshi Aoki ,  Yukio Nakano ,  Masahiro Takatori ,  Toru Kazawa ,  Shinya Sasaki ,  Ryoji Takeyari ,  Hiroyuki Nakano

IPC分类号： H04B10/00 ,  H04B10/02 ,  H04B10/08 ,  H04B10/17 ,  H04J3/14 ,  H04J14/02 ,  H04Q11/00 ,  H04Q11/04

CPC分类号： H04B10/291 ,  H04B10/0773 ,  H04B10/0775 ,  H04B10/0777 ,  H04B10/2912 ,  H04B10/2914 ,  H04B10/299 ,  H04J14/02 ,  H04J14/0221 ,  H04J14/0246 ,  H04J14/0247 ,  H04J14/025 ,  H04J14/0252 ,  H04J14/0283 ,  H04J14/0284 ,  H04J3/085 ,  H04J3/14 ,  H04Q11/0062 ,  H04Q11/0478 ,  H04B2210/003 ,  H04B2210/072 ,  H04B2210/078 ,  H04J14/0226 ,  H04J14/0227 ,  H04J14/0279 ,  H04J14/0286 ,  H04J2203/0051 ,  H04J2203/006 ,  H04Q2011/0069 ,  H04Q2011/0081 ,  H04Q2011/0083

摘要： An optical transmission system accomplishes optical transmission over a long distance by combining a multiplexing line terminal with optical amplifiers, linear repeaters, and regenerators with optical amplifiers combined together. The system also accomplishes the optical transmission over a short distance by directly connecting the linear terminals therebetween, with an electric-to-optic converter replaced by an electric-to-optic converter having a semiconductor amplifier, with an optic-toelectric converter by an optic-to-electric converter having an avalanche photodiode as light receiver, and with no use of any optical booster amplifier and optical preamplifier in the multiplexing line terminal. With these, the optical transmission system can be easily constructed depending on the transmission distance required.

摘要翻译： 光传输系统通过将复用线路终端与光放大器，线性中继器和再生器组合在一起，实现长距离的光传输。 该系统还通过直接连接它们之间的线性端子来实现短距离的光传输，其中电光转换器由具有半导体放大器的电光转换器代替，光电转换器由光学器件 电转换器，其具有雪崩光电二极管作为光接收器，并且在复用线路终端中不使用任何光学增强放大器和光学前置放大器。 利用这些，可以根据所需的传输距离容易地构造光传输系统。

公开(公告)号：US5963555A

公开(公告)日：1999-10-05

申请号：US923873

申请日：1997-09-02

申请人： Akihiko Takase ,  Masahiro Takatori ,  Kazuho Miki ,  Masaru Murakami ,  Koji Wakayama ,  Tetsuro Yoshimoto ,  Masao Kunimoto

发明人： Akihiko Takase ,  Masahiro Takatori ,  Kazuho Miki ,  Masaru Murakami ,  Koji Wakayama ,  Tetsuro Yoshimoto ,  Masao Kunimoto

IPC分类号： H04Q3/00 ,  H04L12/773 ,  H04L12/801 ,  H04L12/815 ,  H04L12/911 ,  H04Q11/04 ,  H04L12/66

CPC分类号： H04L12/5601 ,  H04L49/255 ,  H04L49/606 ,  H04L49/608 ,  H04Q11/0478 ,  H04L2012/5618 ,  H04L2012/5638 ,  H04L2012/5652 ,  H04L2012/5658 ,  H04L2012/5667 ,  H04L2012/5674 ,  H04L2012/5681

摘要： An LAN interface unit and an ATM switch unit cooperate to perform traffic control. A QoS unit monitors circumstances of an input buffer from a multiplexer of the ATM switch by means of a system controller and when an overflow of the input buffer is expected, the LAN interface unit of the multiplexer is instructed to perform traffic control. The LAN interface unit performs traffic control such as limitation of ATM cells inputted in the ATM switch.

公开(公告)号：US5500756A

公开(公告)日：1996-03-19

申请号：US23546

申请日：1993-02-26

申请人： Hideaki Tsushima ,  Shinya Sasaki ,  Yukio Nakano ,  Hiroyuki Nakano ,  Ryoji Tateyari ,  Hironari Matsuda ,  Kenji Tomooka ,  Naohiro Sakakida ,  Shin Nishimura ,  Yoshihiro Yano ,  Youichi Igarashi ,  Satoshi Aoki ,  Masahiro Takatori ,  Tohru Kazawa ,  Yoshihiro Ashi

发明人： Hideaki Tsushima ,  Shinya Sasaki ,  Yukio Nakano ,  Hiroyuki Nakano ,  Ryoji Tateyari ,  Hironari Matsuda ,  Kenji Tomooka ,  Naohiro Sakakida ,  Shin Nishimura ,  Yoshihiro Yano ,  Youichi Igarashi ,  Satoshi Aoki ,  Masahiro Takatori ,  Tohru Kazawa ,  Yoshihiro Ashi

IPC分类号： H04B10/02 ,  H04B10/08 ,  H04B10/17 ,  H04B10/18 ,  H04J14/02 ,  H04Q11/00 ,  H04Q11/04

CPC分类号： H04B10/291 ,  H04B10/0777 ,  H04B10/2537 ,  H04B10/2912 ,  H04B10/2914 ,  H04B10/299 ,  H04J14/02 ,  H04J14/0246 ,  H04J14/025 ,  H04J14/0279 ,  H04Q11/0062 ,  H04Q11/0478 ,  H04B2210/003 ,  H04B2210/071 ,  H04B2210/078 ,  H04J14/0226 ,  H04J14/0227 ,  H04J2203/0051 ,  H04Q2011/0069 ,  H04Q2011/0081 ,  H04Q2011/0083

摘要： An optical repeater for realizing transmission of supervisory information of an optical fiber transmission system without the output power of an optical fiber amplifier being reduced, wherein a supervisory optical transmitter and optical receiver with a wavelength which is similar to the wavelength of the pumping light source of the optical fiber amplifier are mounted, and on the input side of the optical repeater, pumping light is multiplexed in the forward direction and a supervisory optical signal, which is multiplexed in wavelength and transmitted, is demultiplexed simultaneously by the first wavelength multi- and demultiplexer and they are received by the supervisory optical receiver, and on the output side of the optical repeater, pumping light is muitiplexed in the reverse direction and a supervisory optical signal outputted from the supervisory optical transmitter is multiplexed by the second wavelength multi- and demultiplexer.

摘要翻译： 用于实现光纤传输系统的监控信息的传输而不减少光纤放大器的输出功率的光中继器，其中，具有与波长相似的波长的监控光发射机和光接收机， 安装光纤放大器，并且在光中继器的输入侧，泵浦光在正向复用，并且以波长和发送的多路复用的监控光信号由第一波长多路复用器和解复用器同时解复用 并且由监控光接收器接收，在光中继器的输出侧，泵浦光在相反方向多路复用，从监控光发送器输出的监控光信号由第二波长多路复用器多路复用。

公开(公告)号：US5475676A

公开(公告)日：1995-12-12

申请号：US89948

申请日：1993-07-12

申请人： Masahiro Takatori ,  Yukio Nakano ,  Yoshihiro Ashi ,  Hiroyuki Fujita

发明人： Masahiro Takatori ,  Yukio Nakano ,  Yoshihiro Ashi ,  Hiroyuki Fujita

IPC分类号： H04J3/08 ,  H04Q11/04

CPC分类号： H04J3/085

摘要： First stage and third stage four-input four-output space division switches are arranged before and after a second stage time division switch, and two outputs of the first stage space division switch and two inputs of the third stage space division switch are connected by bypassing the time division switch. The time division switch has n control memories. A first control memory stores connection information in a normal state of each path set in the transmission line, a second control memory stores connection information of a first alternative path when failures occur in a path, and an n-th control memory (n is any integer equal or greater than 3) stores connection information of an (n-1)th alternative path, and a control memory corresponding the a failure pattern is selected from the n control memories for each path.

摘要翻译： 第一级和第三级四输入四输出空分开关布置在第二级分时开关之前和之后，第一级空分开关的两个输出和第三级空分开关的两个输入通过旁路连接 时分开关。 时分开关具有n个控制存储器。 第一控制存储器存储在传输线路中设置的每个路径的正常状态的连接信息，当路径中出现故障时，第二控制存储器存储第一替代路径的连接信息，并且第n控制存储器 整数等于或大于3）存储第（n-1）个替代路径的连接信息，并且从每个路径的n个控制存储器中选择与故障模式相对应的控制存储器。

公开(公告)号：US5473598A

公开(公告)日：1995-12-05

申请号：US744513

申请日：1991-08-13

申请人： Masahiro Takatori ,  Yukio Nakano ,  Yoshihiro Ashi ,  Tadayuki Kanno

发明人： Masahiro Takatori ,  Yukio Nakano ,  Yoshihiro Ashi ,  Tadayuki Kanno

IPC分类号： H04L12/70 ,  H04L12/931 ,  H04L12/947 ,  H04J3/26

CPC分类号： H04L49/254 ,  H04L49/256 ,  H04L49/3009 ,  H04L49/3081 ,  H04L49/309 ,  H04L49/552 ,  H04L2012/5627

摘要： A cell routing method and apparatus in an ATM processing apparatus. The ATM processing apparatus has two or more routing tables associated with address filters of an ATM switch to store routing information for indicating the destination of cell output, and two or more conversion tables associated with VPI conversion circuits for replacing VPI (Virtual Path Identifier) or VCI conversion circuits for replacing VCI (Virtual Channel Identifier) to store information for indicating the VPI or VCI obtained after conversion. In an input interface circuit, selection information indicating which routing table and conversion table out of the above described two or more routing tables and two or more conversion tables should be selected is written into an occupied area within a cell. In a switch circuit, the selection information is read and one routing table is selected out of the above described two or more routing tables on the basis of the selection information thus read, and cell routing is thus performed based on information in the selected routing table. Further, in an output interface circuit, selection information contained in the cell is read and one conversion table is selected out of the above described two or more conversion tables on the basis of the selection information thus read, and VPI conversion or VCI conversion is thus executed based on information in the selected conversion table.

摘要翻译： 一种ATM处理装置中的小区路由方法和装置。 ATM处理装置具有与ATM交换机的地址过滤器相关联的两个或多个路由表，以存储用于指示小区输出的目的地的路由信息​​，以及与用于替换VPI（虚拟路径标识符）的VPI转换电路相关联的两个或更多个转换表， 用于替换VCI（虚拟信道标识符）的VCI转换电路以存储用于指示转换后获得的VPI或VCI的信息。 在输入接口电路中，指示应当选择上述两个或多个路由表和两个或多个转换表中的哪个路由表和转换表的选择信息被写入小区内的占用区域。 在开关电路中，读取选择信息，并且根据这样读取的选择信息，从上述两个或多个路由表中选出一个路由表，并且基于所选择的路由表中的信息执行小区路由 。 此外，在输出接口电路中，读取包含在单元中的选择信息，并且根据这样读取的选择信息从上述两个或更多个转换表中选出一个转换表，并且因此进行VPI转换或VCI转换 基于所选转换表中的信息执行。

公开(公告)号：US5271006A

公开(公告)日：1993-12-14

申请号：US663956

申请日：1991-03-19

申请人： Yoshihiro Ashi ,  Tadayuki Kanno ,  Masahiro Takatori ,  Hiromi Ueda

发明人： Yoshihiro Ashi ,  Tadayuki Kanno ,  Masahiro Takatori ,  Hiromi Ueda

IPC分类号： H04J3/06 ,  H04J3/22

CPC分类号： H04J3/0629

摘要： A frame aligner and a method and system for control thereof, in which the frame alignment is executed while assuring TSSI (Time Slot Sequence Integrity). In a system for transmitting a plurality of low-speed signals having a frame structure in a high-speed frame, a plurality of candidates for a write start phase for a frame aligner memory are set, and by accessing a common phase memory storing a write start phase shared by low-speed signals requiring phase matching therebetween of all the low-speed signals stored in the high-speed frame, a write start phase is selected from among the candidates for the write start phase for the frame aligner memory.

摘要翻译： PCT No.PCT / JP90 / 00925 Sec。 371日期1991年3月19日 102（e）1991年3月19日PCT PCT 1990年7月18日PCT公布。 公开号WO91 / 01601 日期1991年2月7日。一种帧对准器及其控制方法和系统，其中在确保TSSI（时隙序列完整性）的同时执行帧对准。 在用于发送具有高速帧中的帧结构的多个低速信号的系统中，设置用于帧对准器存储器的写入开始阶段的多个候选，并且通过访问存储写入的公共相位存储器 低速信号共享的起始相位需要存储在高速帧中的所有低速信号之间的相位匹配，从用于帧对准器存储器的写入开始相位的候选中选择写入开始相位。

公开(公告)号：US5197063A

公开(公告)日：1993-03-23

申请号：US641928

申请日：1991-01-16

申请人： Yukio Nakano ,  Tadayuki Kanno ,  Masahiro Takatori ,  Hiromi Ueda

发明人： Yukio Nakano ,  Tadayuki Kanno ,  Masahiro Takatori ,  Hiromi Ueda

IPC分类号： H04J3/22 ,  H04J3/00 ,  H04J3/16 ,  H04Q11/04

CPC分类号： H04Q11/04 ,  H04J3/1611

摘要： A circuit switching apparatus and method for time division network with various transmission speeds for time-division multiplexing a plurality of circuits including signals at different transmission speeds, transmitting the same onto an input highway, repeatedly recording the transmitted signals in a data memory in a predetermined order, reading respective recorded signals in a predetermined order onto an output highway. An access unit for reading signals from the data memory has an address control memory for storing circuit switching information, a circuit speed control memory for storing transmission speed information for the respective circuits and an address generating section for generating an address for accessing the data memory on the basis of the circuit switching information and the circuit transmission speed information from those memories.

摘要翻译： 一种用于具有各种传输速度的时分网络的电路交换装置和方法，用于对包括不同传输速度的信号的多个电路进行时分复用，将其发送到输入公路上，以预定的方式将数据存储器重复地记录发送的信号 以预定顺序将各个记录信号读出到输出高速公路上。 用于从数据存储器读取信号的访问单元具有用于存储电路切换信息的地址控制存储器，用于存储各个电路的传输速度信息的电路速度控制存储器和用于生成访问数据存储器的地址的地址生成部分 电路切换信息的基础和来自这些存储器的电路传输速度信息。

公开(公告)号：US08483063B2

公开(公告)日：2013-07-09

申请号：US12987665

申请日：2011-01-10

申请人： Masashi Yano ,  Masahiro Takatori ,  Naruhito Nakahara ,  Nodoka Mimura

发明人： Masashi Yano ,  Masahiro Takatori ,  Naruhito Nakahara ,  Nodoka Mimura

IPC分类号： H04J3/16

CPC分类号： H04L47/14 ,  H04L1/1635 ,  H04L1/1854 ,  H04L12/66 ,  H04L43/0894 ,  H04L47/225 ,  H04L47/283 ,  H04L47/323 ,  H04L2001/0097 ,  H04W28/14 ,  H04W88/04 ,  H04W88/08 ,  H04W88/16

摘要： Disclosed is a mobile communication system preventing the transmission of acknowledgements at a burst leading to a decrease in throughput caused by detecting the retransmission and the congestion of packets at the protocol of a transport layer. In a mobile communication system including a mobile terminal and gateway equipment for relaying a packet between a communication partner and the mobile terminal, if the gateway equipment receives the acknowledgement from the mobile terminal, the gateway equipment waits the transmission of the received acknowledgement to the communication partner until the estimated transmission time passes from the time at which the gateway equipment receives the previous acknowledgement from the mobile terminal.

摘要翻译： 公开了一种移动通信系统，其防止在突发情况下发送确认，从而导致通过检测传输层的协议的分组的重传和拥塞而导致的吞吐量的降低。 在包括用于在通信伙伴和移动终端之间中继分组的移动终端和网关设备的移动通信系统中，如果网关设备从移动终端接收到确认，则网关设备等待所接收到的确认传送到通信 伙伴，直到估计传输时间从网关设备从移动终端接收到先前确认的时间过去。

公开(公告)号：US20100182854A1

公开(公告)日：2010-07-22

申请号：US12668336

申请日：2008-06-27

申请人： Masahiro Takatori

发明人： Masahiro Takatori

IPC分类号： G11C7/00

CPC分类号： G11C7/1072 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/222 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

摘要： An operation guarantee system includes a decoder circuit, a comparison circuit, a CPU circuit, a frequency adjustment circuit and a DQ adjustment circuit. The comparison circuit compares a test data signal input from the decoder circuit with an expected value data signal input from the exterior, and detects the presence or absence of an output error in the decoder circuit. The CPU circuit controls the frequency adjustment circuit and the DQ adjustment circuit to vary a frequency of a clock signal input to an external memory and a delay amount of the data signal. In addition, the CPU circuit acquires a result of detection of the comparison circuit under various conditions. Then, the CPU circuit determines an appropriate frequency of the clock signal input to the external memory based on a relationship between the various conditions and the presence or absence of the output error.

摘要翻译： 操作保证系统包括解码器电路，比较电路，CPU电路，频率调整电路和DQ调整电路。 比较电路将从解码器电路输入的测试数据信号与从外部输入的期望值数据信号进行比较，并且检测解码器电路中是否存在输出错误。 CPU电路控制频率调整电路和DQ调整电路，以改变输入到外部存储器的时钟信号的频率和数据信号的延迟量。 此外，CPU电路在各种条件下获取比较电路的检测结果。 然后，CPU电路基于各种条件与输出错误的存在或不存在之间的关系来确定输入到外部存储器的时钟信号的适当频率。

公开(公告)号：US20080205016A1

公开(公告)日：2008-08-28

申请号：US11908726

申请日：2006-03-15

申请人： Masahiro Takatori ,  Yukihiro Ishimaru

发明人： Masahiro Takatori ,  Yukihiro Ishimaru

IPC分类号： H05K1/14

CPC分类号： H01L25/0652 ,  H01L23/5385 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0268 ,  H05K1/112 ,  H05K1/117 ,  H05K1/185 ,  H05K3/4611 ,  H05K2201/0919 ,  H05K2201/09845 ,  H01L2924/00 ,  H01L2924/00012

摘要： A module board has a configuration in which a first circuit board, a first composite sheet, a second circuit board, a second composite sheet, and a third circuit board are laminated in this order. Inspection terminals are arranged in a matrix shape in a predetermined region on an upper surface of the third circuit board. Electronic components are mounted on the first and second circuit boards. The inspection terminals are electrically connected to the electronic components mounted on the first and second circuit boards through vias and wiring patterns.

摘要翻译： 模块板具有以下顺序构造第一电路板，第一复合片，第二电路板，第二复合片和第三电路板。 检查端子在第三电路板的上表面上的预定区域中以矩阵形状布置。 电子部件安装在第一和第二电路板上。 检查端子通过通孔和布线图形电连接到安装在第一和第二电路板上的电子部件。