公开(公告)号：US20100155992A1

公开(公告)日：2010-06-24

申请号：US12644399

申请日：2009-12-22

申请人： Nobuyuki Kurashima ,  Toshio Kobayashi

发明人： Nobuyuki Kurashima ,  Toshio Kobayashi

IPC分类号： B29C45/14

CPC分类号： B29C45/14655 ,  B29C45/0025 ,  B29C45/02 ,  B29C45/56 ,  B29C45/77 ,  B29C2945/76498 ,  B29C2945/76735 ,  B29C2945/76765 ,  B29C2945/76859 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014

摘要： A mold resin molding method is provided with: providing a semiconductor device including a first wiring board and a second wiring board electrically connected to the first wiring board through a solder ball; providing a metal mold including a die plate which is independently provided to enable an approach/separation to/from the second wiring board; inserting the semiconductor device into a cavity of the metal mold; abutting the die plate on a surface side of the second wiring board through a release film; injecting a mold resin in a void between the first wiring board and the second wiring board while applying a first pressure from the die plate to the second wiring board; and further injecting the mold resin in the void while applying a second pressure which is higher than the first pressure from the die plate to the second wiring board.

摘要翻译： 模具树脂成型方法具有：提供包括第一布线板和第二布线板的半导体器件，所述第一布线板和第二布线板通过焊球与第一布线板电连接; 提供包括模板的金属模具，所述模具板独立地设置成能够进入/离开所述第二布线板; 将半导体器件插入到金属模具的空腔中; 通过脱模膜将模板抵靠在第二配线基板的表面侧; 在第一配线板和第二配线板之间的空隙中注入模塑树脂，同时从模板施加第一压力到第二配线板; 并且在将来自模板的第一压力高于第二压接力的第二压力施加到第二配线基板的同时，将模具树脂进一步注入到空隙中。

公开(公告)号：US20100025081A1

公开(公告)日：2010-02-04

申请号：US12492560

申请日：2009-06-26

申请人： Tadashi Arai ,  Toshio Kobayashi

发明人： Tadashi Arai ,  Toshio Kobayashi

IPC分类号： H05K1/16 ,  H05K1/11 ,  H05K1/09

CPC分类号： H01L23/49822 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49833 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2224/0401

摘要： A wiring substrate includes a frame-shaped reinforcing plate in which an opening portion is provided in a center portion, an interposer arranged in the opening portion of the reinforcing plate and having such a structure that a wiring layer connected mutually via a through electrode is formed on both surface sides of a substrate respectively, a resin portion filled between a side surface of the interposer and a side surface of the opening portion of the reinforcing plate, and coupling the interposer and the reinforcing plate, and an n-layered (n is an integer of 1 or more) lower wiring layer connected the wiring layer on the lower surface side of the interposer to extend from the interposer to an outer area.

摘要翻译： 布线基板包括在中心部分设置有开口部的框状加强板，布置在加强板的开口部中的内插件，并且具有通过贯通电极相互连接的布线层的结构 在衬底的两个表面侧分别填充有插入件的侧表面和加强板的开口部分的侧表面之间的树脂部分，并且连接插入件和加强板，并且n层（n是 1个以上的整数）下布线层，其连接在插入件的下表面侧上的布线层，以从插入件延伸到外部区域。

公开(公告)号：US07605424B2

公开(公告)日：2009-10-20

申请号：US11846802

申请日：2007-08-29

申请人： Tsutomu Imoto ,  Toshio Kobayashi ,  Takayoshi Kato

发明人： Tsutomu Imoto ,  Toshio Kobayashi ,  Takayoshi Kato

IPC分类号： H01L29/94

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L29/1037 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device including: a semiconductor region having a first semiconductor face and a second semiconductor face connected to the first semiconductor face and having an inclination with respect to the first semiconductor face; a gate insulating film formed on the first and on the second semiconductor faces; a gate electrode formed on the gate insulating film including a part on a boundary between the first semiconductor face and the second semiconductor face; a source impurity region formed in the semiconductor region so as to overlap the gate electrode within the first semiconductor face with the gate insulating film interposed between the source impurity region and the gate electrode; and a drain impurity region formed in the semiconductor region directly under the second semiconductor face at least.

摘要翻译： 一种半导体器件，包括：半导体区域，具有连接到第一半导体表面并且具有相对于第一半导体表面的倾斜的第一半导体面和第二半导体面; 形成在所述第一和第二半导体面上的栅极绝缘膜; 形成在所述栅极绝缘膜上的栅极，所述栅极绝缘膜包括在所述第一半导体面和所述第二半导体面之间的边界上的一部分; 源极杂质区，形成在所述半导体区域中，以与所述栅极绝缘膜插入在所述源极杂质区域和所述栅极电极之间，与所述第一半导体面内的所述栅电极重叠; 以及至少在第二半导体面的正下方的半导体区域中形成的漏极杂质区域。

公开(公告)号：US20080155820A1

公开(公告)日：2008-07-03

申请号：US11984004

申请日：2007-11-13

申请人： Tadashi Arai ,  Toshio Kobayashi

发明人： Tadashi Arai ,  Toshio Kobayashi

IPC分类号： H01L23/48 ,  H05K3/36

CPC分类号： H01L23/3128 ,  H01L21/565 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/50 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/19041 ,  Y10T29/49126 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： In a wiring substrate according to the present invention, a base wiring board is constructed by stacking a plurality of unit wiring boards each having wiring patterns which enable an electrical connection between upper and lower sides, in a state that the plurality of unit wiring boards are connected to each other via a connection terminal, and a silicon interposer is stacked on the base wiring board via a connection terminal, and a resin portion is filled in a gap between the plurality of unit wiring boards as well as a gap between the base wiring board and the silicon interposer, and a resin portion serves as a substrate which integrates the base wiring board and the silicon interposer.

摘要翻译： 在本发明的布线基板中，通过在多个单元配线基板为多个单元配线基板的状态下，堆叠多个单元配线基板，该多个单元配线基板具有能够在上下侧之间进行电连接的布线图案 通过连接端子彼此连接，并且硅插入件经由连接端子堆叠在基底布线板上，树脂部分填充在多个单元布线板之间的间隙以及基布线 板和硅插入件，树脂部分用作将基布线板和硅插入件集成的基板。

公开(公告)号：US07074706B2

公开(公告)日：2006-07-11

申请号：US11112538

申请日：2005-04-22

申请人： Junichi Aoyama ,  Toshio Kobayashi

发明人： Junichi Aoyama ,  Toshio Kobayashi

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/76807 ,  H01L23/5221 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a semiconductor device in which a problem such as a thermal diffusion defect in a hollow wiring technique can be solved. In the semiconductor device, a gap is formed between wirings formed on a substrate, and the gap is filled with a gas having a thermal conductivity equal to or higher than three times that of air at 0° C.

公开(公告)号：US07074675B2

公开(公告)日：2006-07-11

申请号：US11043671

申请日：2005-01-26

申请人： Kazumasa Nomoto ,  Toshio Kobayashi

发明人： Kazumasa Nomoto ,  Toshio Kobayashi

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/792 ,  Y10S438/954

摘要： A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive semiconductor to function as a source or a drain, a gate dielectric film containing therein charge storage means which is spatially discrete and being formed on the first conductive semiconductor so as to coat at least a sidewall of each of the steps, and a gate electrode formed on the gate dielectric film. Accordingly, there are provided a non-volatile semiconductor memory device which suffers almost no deterioration in the properties and can perform the operation of recording of 2 bits per unit memory device even when the size of the semiconductor memory device in the semiconductor substrate is scaled down, and a process for fabricating the non-volatile semiconductor memory device.

公开(公告)号：US07057233B2

公开(公告)日：2006-06-06

申请号：US11093377

申请日：2005-03-30

申请人： Kazumasa Nomoto ,  Toshio Kobayashi

发明人： Kazumasa Nomoto ,  Toshio Kobayashi

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/792 ,  Y10S438/954

摘要： A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive semiconductor to function as a source or a drain, a gate dielectric film containing therein charge storage means which is spatially discrete and being formed on the first conductive semiconductor so as to coat at least a sidewall of each of the steps, and a gate electrode formed on the gate dielectric film. Accordingly, there are provided a non-volatile semiconductor memory device which suffers almost no deterioration in the properties and can perform the operation of recording of 2 bits per unit memory device even when the size of the semiconductor memory device in the semiconductor substrate is scaled down, and a process for fabricating the non-volatile semiconductor memory device.

公开(公告)号：US07012329B2

公开(公告)日：2006-03-14

申请号：US11098503

申请日：2005-04-05

申请人： Kazumasa Nomoto ,  Toshio Kobayashi ,  Akihiro Nakamura ,  Ichiro Fujiwara ,  Toshio Terano

发明人： Kazumasa Nomoto ,  Toshio Kobayashi ,  Akihiro Nakamura ,  Ichiro Fujiwara ,  Toshio Terano

IPC分类号： H01L29/76

CPC分类号： H01L27/11568 ,  H01L21/2815 ,  H01L27/115 ,  H01L29/6656

摘要： A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.

公开(公告)号：US07008509B1

公开(公告)日：2006-03-07

申请号：US10048446

申请日：2000-08-04

申请人： Kenichi Otani ,  Toshio Kobayashi ,  Toshiharu Togashi ,  Shingo Odajima ,  Tokihito Sono ,  Masayuki Osaki ,  Hiromichi Kimbara ,  Atsushi Sato

发明人： Kenichi Otani ,  Toshio Kobayashi ,  Toshiharu Togashi ,  Shingo Odajima ,  Tokihito Sono ,  Masayuki Osaki ,  Hiromichi Kimbara ,  Atsushi Sato

IPC分类号： D21F13/00

CPC分类号： D21J7/00 ,  B65D2501/0045 ,  D21J3/10 ,  Y10T428/1303

摘要： A molded body formed with pulp mold having projected lines corresponding to a slit-shaped vent package part, capable of being provided by paper-making/dewatering, using a paper making mold, a slurry having fibers dispersed in a liquid so as to obtain a three-dimensional fiber wetted laminated body, moving the laminated body to a dry mold having an inner surface with the slit-shaped vent package, and pressing and drying that laminated body.

摘要翻译： 一种成型体，其形成有纸模，其具有对应于通过造纸/脱水提供的狭缝状排气口包装部分的突出线，使用造纸模具，具有分散在液体中的纤维的浆料，以获得 三维纤维湿润层叠体，将层叠体移动到具有狭缝状排气口封装的内表面的干燥模具，并且对层叠体进行加压干燥。

公开(公告)号：US20060014907A1

公开(公告)日：2006-01-19

申请号：US10527696

申请日：2003-06-03

申请人： Seiichiro Hirata ,  Shoji Shirahama ,  Toshio Kobayashi ,  Ichirou Aoyama

发明人： Seiichiro Hirata ,  Shoji Shirahama ,  Toshio Kobayashi ,  Ichirou Aoyama

IPC分类号： C08G63/91 ,  C08L67/08

CPC分类号： E04C5/08 ,  C08G59/18 ,  C08K5/098 ,  C09D163/10 ,  C09D167/08

摘要： Disclosed is a coating composition for a tendon for prestressed concrete; wherein being applied on the surface of the tendon for a tendon for prestressed concrete; comprising oxidation-curing type resin modified with fatty acid, and metal catalyst to promote the curing of the resin; and curing time thereof is adjusted so that tensioning by the tendon can be exerted 30 days or later after casting of the concrete. The coating composition can be used safely almost without cutaneous stimulation, and enable effective tensioning even after hardening of the concrete when applied to massive concrete structure. Further, the coating composition exhibits excellent storage stability.

摘要翻译： 公开了用于预应力混凝土的腱的涂料组合物; 其中施加在用于预应力混凝土的腱的腱的表面上; 包括用脂肪酸改性的氧化固化型树脂和促进树脂固化的金属催化剂; 并且调节其固化时间，使得在浇筑混凝土之后30天或更长时间可以施加腱的张紧。 涂料组合物几乎可以安全地使用，无需皮肤刺激，即使在施加到大块混凝土结构时，混凝土硬化后也能有效拉伸。 此外，涂料组合物表现出优异的储存稳定性。