公开(公告)号：US07495990B2

公开(公告)日：2009-02-24

申请号：US11806721

申请日：2007-06-04

申请人： Kazufumi Komura ,  Yoshiharu Kato ,  Satoru Kawamoto

发明人： Kazufumi Komura ,  Yoshiharu Kato ,  Satoru Kawamoto

IPC分类号： G11C8/00

CPC分类号： G11C11/4094 ,  G11C11/4076 ,  G11C2207/005

摘要： It is an object to provide a semiconductor memory device that can conduct the equalizing operation of bit lines with a low current consumption while maintaining a normal accessing speed and the chip area, and a control method thereof. In a semiconductor memory device of the shared sense amplification system, in a predetermined number of times which is (k−1) times or less among k-times of continuous word line selections of a selected memory block, the bit line separation gate of the unselected memory block is rendered conductive in the active period of the equalizing unit after the word line selection. Also, a circuit that equalizes a wiring higher in the capacity component is driven by a higher voltage level according to the wiring capacity component of the sense amplification power supply line and the bit lines, to thereby equalize the power supply line and the bit line in the equal time, thereby being capable of preventing the short-circuiting within the sense amplifier.

摘要翻译： 本发明的目的是提供一种半导体存储器件及其控制方法，该半导体存储器件可以在保持正常访问速度和芯片面积的同时以低电流消耗进行位线的均衡操作。 在共享读出放大系统的半导体存储器件中，在所选择的存储器块的连续字线选择的k次之间的预定次数（k-1）倍以下的情况下，位线分离门 未选择的存储块在字线选择之后的均衡单元的有效周期内变为导通。 此外，根据感测放大电源线和位线的布线电容分量，通过较高的电压电平驱动均衡电容分量较高的布线的电路，从而使电源线和位线的均匀化 相等的时间，从而能够防止读出放大器内的短路。

公开(公告)号：US07440038B2

公开(公告)日：2008-10-21

申请号：US11166395

申请日：2005-06-23

申请人： Yoshiharu Kato

发明人： Yoshiharu Kato

IPC分类号： H04N5/64

CPC分类号： F16M11/2014 ,  F16M11/10 ,  F16M2200/08 ,  H04N5/64 ,  Y10S248/919

摘要： There is disclosed a liquid crystal display apparatus including a main body and a swivel mechanism, where the main body is capable of smoothly swiveling. A countersunk hole is formed in a bottom plate member as follows: When a through-hole for inserting a screw is formed in a metal sheet to be a bottom plate member, there is also concurrently formed an accommodating hole for accommodating flow of the material forming the metal sheet upon plastic forming or pressing which is performed subsequently for forming a countersink, and then the countersink is formed at an open end of the through-hole by pressing. It is preferable that a plurality of the accommodating holes are formed around the through-hole.

摘要翻译： 公开了一种包括主体和旋转机构的液晶显示装置，其中主体能够平稳地旋转。 在底板构件中形成有埋头孔，如下所述：当金属板中形成用于插入螺钉的通孔作为底板构件时，还形成有用于容纳形成材料的流动的容纳孔 金属片在塑性成形或压制时随后进行以形成埋头孔，然后通过压制在通孔的开口端形成埋头孔。 优选地，在通孔周围形成有多个容纳孔。

公开(公告)号：US20070091678A1

公开(公告)日：2007-04-26

申请号：US11583129

申请日：2006-10-19

申请人： Yoshiharu Kato ,  Yoshihiro Takemae ,  Toshio Ogawa ,  Tetsuhiko Endoh ,  Yoshinori Okajima

发明人： Yoshiharu Kato ,  Yoshihiro Takemae ,  Toshio Ogawa ,  Tetsuhiko Endoh ,  Yoshinori Okajima

IPC分类号： G11C16/06

CPC分类号： G11C16/32 ,  G06F11/1068 ,  G11C7/1006 ,  G11C2029/0411 ,  G11C2207/104

摘要： A volatile memory has a volatile additional area for storing an error correction code for a nonvolatile memory. Data stored in the nonvolatile memory are transferred to the volatile memory together with the error correction code without making an error correction. Thus, data transfer time from the nonvolatile memory to the volatile memory can be shortened. As a result, it is possible to shorten the time from beginning of the data transfer from the nonvolatile memory to the volatile memory to a point at which data becomes accessible.

摘要翻译： 易失性存储器具有用于存储用于非易失性存储器的纠错码的易失性附加区域。 存储在非易失性存储器中的数据与错误校正码一起传送到易失性存储器，而不进行纠错。 因此，可以缩短从非易失性存储器到易失性存储器的数据传送时间。 结果，可以缩短从非易失性存储器到易失性存储器的数据传输开始到数据可访问的时间。

公开(公告)号：US07206246B2

公开(公告)日：2007-04-17

申请号：US11249454

申请日：2005-10-14

申请人： Masami Nakashima ,  Yoshiharu Kato ,  Kazufumi Komura

发明人： Masami Nakashima ,  Yoshiharu Kato ,  Kazufumi Komura

IPC分类号： G11C7/00

CPC分类号： G11C29/50016 ,  G11C8/18 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40603 ,  G11C29/028 ,  G11C29/50 ,  G11C29/783 ,  G11C2207/2227 ,  G11C2211/4061 ,  G11C2211/4067

摘要： The present invention provides a semiconductor memory device which reduces current consumption in a standby state owing to a suitable refresh-thinning-out function, and a refresh control method thereof. When the refresh-thinning-out function is added while a refresh operation and an external access operation are being executed independently of each other, a refresh address counter outputs a refresh address Add(C) and inputs predetermined high-order bits thereof to a refresh-thinning-out control as a high-order refresh address Add(C) (m), where judgment as to whether the refresh operation is performed, is made. A refresh permission signal RFEN corresponding to the result of judgment is inputted to a word driver to activate and control the word driver. The process of judgment by the refresh-thinning-out control circuit can be embedded in an access time of a row system.

公开(公告)号：US20060226529A1

公开(公告)日：2006-10-12

申请号：US11448863

申请日：2006-06-08

申请人： Yoshiharu Kato ,  Satoru Kawamoto ,  Fumihiko Taniguchi ,  Tetsuya Hiraoka ,  Akira Takashima

发明人： Yoshiharu Kato ,  Satoru Kawamoto ,  Fumihiko Taniguchi ,  Tetsuya Hiraoka ,  Akira Takashima

IPC分类号： H01L23/02

CPC分类号： H01L22/22 ,  H01L23/544 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5448 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48135 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/4943 ,  H01L2224/73265 ,  H01L2224/8513 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01039 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： The present invention relates to a semiconductor device having an MCP (Multi Chip Package) structure in which a plurality of semiconductor chips are mounted in the same package, a manufacturing method therefor and a semiconductor substrate used therein. Atop a first semiconductor chip that is a memory chip is mounted a second semiconductor chip that is a logic chip, with a first functional chip and a second functional chip that together form the first semiconductor chip being joined together via an unsliced scribe line. Additionally, a first functional chip and a second functional chip are given the same chip composition (32-bit memory) and respectively rotated 180 degrees relative to each other. These configurations are intended to improve performance, reduce costs and improve yield.

公开(公告)号：US07028235B1

公开(公告)日：2006-04-11

申请号：US09494953

申请日：2000-02-01

申请人： Yoshiharu Kato

发明人： Yoshiharu Kato

IPC分类号： G01R31/28

CPC分类号： G11C29/025 ,  G01R31/2853 ,  G11C29/02 ,  G11C29/36

摘要： A method of testing an electronic device including first and second semiconductor devices connected to each other with a plurality of bus lines. First, the first semiconductor device supplies a selected one of the bus lines with a first logical output signal. Then, the second semiconductor device acquires a first bus line signal from the selected bus line. The second semiconductor device inverts the first bus line signal to generate a second logical output signal. The second semiconductor device transmits the second logical output signal to the first semiconductor device. The first semiconductor device receives a second bus line signal from the selected bus line. The first semiconductor device compares the first logical output signal and the second bus line signal to detect a connection between the first semiconductor device and the second semiconductor device.

摘要翻译： 一种测试电子设备的方法，该电子设备包括用多个总线线路彼此连接的第一和第二半导体器件。 首先，第一半导体器件向所选择的总线线路提供第一逻辑输出信号。 然后，第二半导体器件从所选择的总线获取第一总线信号。 第二半导体器件使第一总线信号反相以产生第二逻辑输出信号。 第二半导体器件将第二逻辑输出信号发送到第一半导体器件。 第一半导体器件从所选择的总线接收第二总线信号。 第一半导体器件比较第一逻辑输出信号和第二总线信号以检测第一半导体器件和第二半导体器件之间的连接。

公开(公告)号：US20060001783A1

公开(公告)日：2006-01-05

申请号：US11166469

申请日：2005-06-23

申请人： Yoshiharu Kato

发明人： Yoshiharu Kato

IPC分类号： H04N5/64

CPC分类号： H04N5/64 ,  F16M11/10 ,  F16M11/2014 ,  F16M2200/08

摘要： A liquid crystal display apparatus including a tilt mechanism, which is capable of preventing an inadvertent insertion of a finger of a user in a groove of a bracket of the tilt mechanism even while a cover for concealing the bracket is removed, wherein provided is a washer-like member or inadvertent-insertion preventer which has a through-hole or perforated portion through which a pawl formed in a mainbody bracket or one of two brackets is inserted, and is attached to the pawl at a position to contact a stand bracket or the other of the two brackets, by inserting the pawl through the through-hole. The washer-like member is preferably made of a plastic and sandwiched between the two brackets.

摘要翻译： 一种液晶显示装置，包括倾斜机构，其能够防止用户的手指无意插入倾斜机构的支架的凹槽中，即使在用于隐藏托架的盖子被移除时，其中设置有垫圈 其具有通孔或穿孔部分，通过该通孔或穿孔部分形成在主体托架中的​​棘爪或两个托架中的一个托架中的棘爪，并且在与支架支架或者支架支架接触的位置处附接到棘爪 通过将棘爪插入通孔中，两个支架中的另一个。 垫圈状构件优选地由塑料制成并夹在两个托架之间。

公开(公告)号：US20050169060A1

公开(公告)日：2005-08-04

申请号：US11090661

申请日：2005-03-28

申请人： Yoshiharu Kato

发明人： Yoshiharu Kato

IPC分类号： G01R31/28 ,  G11C5/00 ,  G11C16/20 ,  G11C29/44 ,  H01L21/822 ,  H01L27/04 ,  H04N5/232 ,  H04N5/235

CPC分类号： G11C16/20 ,  G11C29/1201 ,  G11C29/44 ,  G11C2029/4402 ,  H04N5/232 ,  H04N5/2353

摘要： It is intended to provide a semiconductor integrated circuit device permitting reading of information specific to chips within the mounted chips while restraining the increase in the total number of terminals of the package and enabling the area of circuits required for reading information specific to chips to be made smaller than that according to the prior art, and a control method therefor. The same terminal is used as the external terminal to which the pulse signals are inputted and the external terminal from which the chip-specific information is outputted. Also, the external terminal for inputting/outputting required power supply in the normal operation mode and the external terminal for reading chip-specific information in the information reading mode are used in common. The increase in the number of external terminals can be thereby restrained. Moreover, the counter unit is shared between functional circuits and the comparative decision unit. This can serve to restrain the increase in chip area.

摘要翻译： 旨在提供一种半导体集成电路装置，允许读取安装的芯片内的芯片的信息，同时抑制封装的端子总数的增加，并且使得能够制作读取芯片特有的信息所需的电路区域 小于根据现有技术的控制方法。 使用相同的端子作为输入脉冲信号的外部端子和从其输出芯片特定信息的外部端子。 此外，共同使用用于在正常操作模式下输入/输出所需电源的外部端子和用于在信息读取模式中读取芯片特定信息的外部端子。 由此可以抑制外部端子的数量的增加。 此外，计数器单元在功能电路和比较判定单元之间共享。 这可以抑制芯片面积的增加。

公开(公告)号：US06717868B2

公开(公告)日：2004-04-06

申请号：US10260286

申请日：2002-10-01

申请人： Yoshiharu Kato ,  Satoru Kawamoto

发明人： Yoshiharu Kato ,  Satoru Kawamoto

IPC分类号： G11C700

CPC分类号： G11C7/22 ,  G11C11/4076 ,  G11C11/408 ,  G11C2207/002 ,  G11C2207/2281

摘要： There is provided an inventive semiconductor memory device and control method thereof capable of preventing shift operation to deactivated state and data access due to transition of address signals from occurring concurrently without accompanying delay of access time, thereby to prevent data-holding characteristic of memory cell from deteriorating. A column selecting circuit 16 is deactivated based on an input signal EXBn outputted to a glitch canceller 20 prior to precharge signal PRE so as to prevent selection of a column selecting signal CLn and deactivation of a word line WL from occurring concurrently. This manner substitutes for taking delay time &tgr;D that is to be added to signals CAGn from which glitch noises due to transition of address CAn are eliminated. Thereby, address-access time, namely, from transition of address CAn till selection of a column selecting signal CLn, is kept in the shortest access time tAAX0 and the column selecting circuit 16 can be deactivated prior to deactivation of the word line WL.

摘要翻译： 提供了一种本发明的半导体存储器件及其控制方法，其能够防止由于地址信号的转变而导致的去活动状态和数据访问而不伴随访问时间的延迟，从而防止存储器单元的数据保持特性 恶化 基于在预充电信号PRE之前输出到毛刺消除器20的输入信号EXBn，列选择电路16被去激活，以防止同时选择列选择信号CLn和字线WL的停止。 这种方式代替了将被添加到信号CAGn的延迟时间tauD，由此消除了由于地址CAn的转换导致的毛刺噪声。 因此，地址访问时间，即从地址CAn的转换到列选择信号CLn的选择，被保持在最短访问时间tAAX0中，并且列选择电路16可以在字线WL的去激活之前去活。

公开(公告)号：US06678804B1

公开(公告)日：2004-01-13

申请号：US09545079

申请日：2000-04-07

申请人： Kazuo Funatogawa ,  Yoshiharu Kato ,  Masanobu Ogata

发明人： Kazuo Funatogawa ,  Yoshiharu Kato ,  Masanobu Ogata

IPC分类号： G06F1200

CPC分类号： G06T1/60

摘要： The present invention relates to an apparatus and method for reducing the frequency with which memory is accessed in graphic printing or the like. If a CPU 100 reads image data from a buffer block where data has not been written, a memory controller 12 does not read the image data from a image buffer 140, but sends back initializing data stored beforehand. If image data is going to be written for the first time in a buffer block, the memory controller 12 stores and manages this image data, first writes the initializing data in this buffer block, and thereafter writes the image data. If a read request or a write request occurs to a buffer block where data has already been written, the memory controller 12 reads or writes data as requested.

摘要翻译： 本发明涉及一种用于在图形打印等中降低访问存储器的频率的装置和方法。 如果CPU 100从尚未写入数据的缓冲块读取图像数据，则存储器控制器12不从图像缓冲器140读取图像数据，而是将预先存储的初始化数据发回。 如果图像数据将首先在缓冲块中写入，则存储器控制器12存储和管理该图像数据，首先将该初始化数据写入该缓冲块中，然后写入图像数据。 如果对已经写入数据的缓冲器块发生读取请求或写入请求，则存储器控制器12根据请求读取或写入数据。