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公开(公告)号：US20150162089A1
公开(公告)日：2015-06-11
申请号：US14626208
申请日：2015-02-19
CPC分类号： G11C16/107 , G06F12/0246 , G06F12/06 , G06F2206/1014 , G06F2212/7201 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C13/0002 , G11C14/0018 , G11C14/0045 , G11C16/00 , G11C16/0483 , G11C16/10 , G11C2211/5641 , H03M7/14
摘要： The present disclosure includes methods and apparatuses for mapping between program states and data patterns. One method includes: programming a group of G memory cells such that a combination of respective program states of the group maps to a constellation point corresponding to a received N unit data pattern, the group used to store N/G units of data per memory cell; wherein the constellation point is one of a number of constellation points of a constellation associated with mapping respective program state combinations of the group of memory cells to N unit data patterns; and wherein the constellation comprises a first mapping shell and a second mapping shell, the constellation points corresponding to the respective first and second mapping shells determined, at least partially, based on a polynomial expression of order equal to G.
摘要翻译： 本公开包括用于在程序状态和数据模式之间进行映射的方法和装置。 一种方法包括：对一组G存储器单元进行编程，使得该组的各个程序状态的组合映射到与接收到的N单位数据模式对应的星座点，该组用于存储每个存储单元的N / G个数据单元 ; 其中所述星座点是与将所述存储器单元组的各个程序状态组合映射到N个单位数据模式相关联的星座的多个星座点中的一个; 并且其中所述星座包括第一映射外壳和第二映射外壳，所述星座点对应于相应的第一和第二映射外壳，至少部分地基于等于G的等级的多项式表达式确定。
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公开(公告)号：US20140351491A1
公开(公告)日：2014-11-27
申请号：US14304420
申请日：2014-06-13
CPC分类号： G11C16/107 , G06F12/0246 , G06F12/06 , G06F2206/1014 , G06F2212/7201 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C13/0002 , G11C14/0018 , G11C14/0045 , G11C16/00 , G11C16/0483 , G11C16/10 , G11C2211/5641 , H03M7/14
摘要： The present disclosure includes methods and apparatuses for mapping between program states and data patterns. One method includes: programming a group of G memory cells such that a combination of respective program states of the group maps to a constellation point corresponding to a received N unit data pattern, the group used to store N/G units of data per memory cell; wherein the constellation point is one of a number of constellation points of a constellation associated with mapping respective program state combinations of the group of memory cells to N unit data patterns; and wherein the constellation comprises a first mapping shell and a second mapping shell, the constellation points corresponding to the respective first and second mapping shells determined, at least partially, based on a polynomial expression of order equal to G.
摘要翻译： 本公开包括用于在程序状态和数据模式之间进行映射的方法和装置。 一种方法包括：对一组G存储器单元进行编程，使得该组的各个程序状态的组合映射到与接收到的N单位数据模式对应的星座点，该组用于存储每个存储单元的N / G个数据单元 ; 其中所述星座点是与将所述存储器单元组的各个程序状态组合映射到N个单位数据模式相关联的星座的多个星座点中的一个; 并且其中所述星座包括第一映射外壳和第二映射外壳，所述星座点对应于相应的第一和第二映射外壳，至少部分地基于等于G的等级的多项式表达式确定。
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公开(公告)号：US20140208054A1
公开(公告)日：2014-07-24
申请号：US13746181
申请日：2013-01-21
IPC分类号： G06F12/02
CPC分类号： G11C11/5628 , G06F3/06 , G06F11/102 , G06F11/104 , G06F12/02 , G11C11/5642 , G11C16/0483 , G11C29/16 , G11C2211/5641
摘要： Apparatuses and methods for determining soft data for fractional digit memory cells are provided. One example apparatus can include a controller to determine states of memory cells of a group of memory cells operated as fractional digit memory cells, and determine soft data based, at least partially, on dimensions to which particular memory cells correspond with respect to the group of memory cells, determined states of the memory cells with respect to a state adjacent a state corresponding to a swapping shell, and whether a particular memory cell is a candidate for swapping.
摘要翻译： 提供了用于确定分数位存储单元的软数据的装置和方法。 一个示例性设备可以包括控制器，以确定作为分数位存储器单元操作的一组存储器单元的存储器单元的状态，以及至少部分地基于与特定存储器单元相对应的特定存储器单元对应的维度来确定软数据 存储器单元，相对于与交换壳相对应的状态相邻的状态的存储器单元的确定状态，以及特定存储器单元是否是用于交换的候选。
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公开(公告)号：US20240331778A1
公开(公告)日：2024-10-03
申请号：US18744146
申请日：2024-06-14
CPC分类号： G11C16/26 , G06F3/0604 , G06F3/0655 , G06F3/0679 , G11C16/3459 , G11C16/0483
摘要： Embodiments disclosed can include selecting a target read window budget (RWB) increase and identifying a set of aggressor memory cells. They can also include generating a list of programming level states for the set of aggressor memory cells and identifying, in the list, an entry associated with a maximum RWB increase that is greater than or equal to the target RWB increase. They can further include responsive to identifying the entry with the total number of bits associated with a maximum RWB increase that is greater than or equal to the target RWB increase, modifying a parameter of the memory access operation with the adjustment associated with the identified entry.
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65.发明授权公开(公告)号：US12087374B2
公开(公告)日：2024-09-10
申请号：US17884107
申请日：2022-08-09
CPC分类号： G11C16/3459 , G11C16/08 , G11C16/102 , G11C16/26
摘要： Embodiments disclosed can include determining, for a wordline of the plurality of wordlines, a target read window budget (RWB) increase, wherein the target RWB increase corresponds to a maximum RWB increase associated with using a different PV voltage offset for each respective programming level of a memory cell. Embodiments can also include segmenting the plurality of wordlines into one or more wordline groups, wherein each wordline group comprises one or more wordlines. Embodiments can further include determining, for each wordline group, a target adjustment to a parameter of a memory access operation that is performed with respect to a memory cell associated with a wordline of the wordline group. Embodiments can include determining an aggregate RWB increase for the block in view of the target adjustment to the parameter of the memory access operation. Embodiments can further include determining that the aggregate RWB increase for the block satisfies a threshold range associated with the target RWB increase. Embodiments can also include modifying the parameter of the memory access operation according to the target adjustment.
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公开(公告)号：US12072762B2
公开(公告)日：2024-08-27
申请号：US17884076
申请日：2022-08-09
CPC分类号： G06F11/1044 , G11C29/08
摘要： Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising selecting a source set of memory cells of the memory device, performing a data integrity check on the source set of memory cells to obtain a data integrity metric value; responsive to determining that a data integrity metric value satisfies the threshold criterion, performing a first error-handling operation on the data stored on the source set of memory cells; responsive to determining that the first error-handling operation fails to correct the data, performing a second error-handling operation on the data; and responsive to determining that the second error-handling operation corrected the data, causing the memory device to copy the corrected data to a destination set of memory cells of the memory device.
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公开(公告)号：US12067290B2
公开(公告)日：2024-08-20
申请号：US17591406
申请日：2022-02-02
发明人： Kishore Kumar Muchherla , Violante Moschiano , Akira Goda , Jeffrey S. McNeil , Jung Sheng Hoei , Sivagnanam Parthasarathy , James Fitzpatrick , Patrick R. Khayat
IPC分类号： G06F3/06
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0679
摘要： Control logic in a memory device receives a request to read data from a memory array of a memory device, the request comprising an indication of a segment of the memory array where the data is stored, and determines whether a write temperature associated with the data is stored in a flag byte corresponding to the segment of the memory array. Responsive to determining that the write temperature associated with the data is stored in the flag byte, the control logic determines a cross-temperature for the data based on the write temperature and a read temperature at a time when the request to read the data is received, determines a program/erase cycle count associated with the segment of the memory array, and determines, based on the cross-temperature and the program/erase cycle count, whether to perform a corrective action to calibrate a read voltage level to be applied to the memory array to read the data from the segment.
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公开(公告)号：US20240134571A1
公开(公告)日：2024-04-25
申请号：US18401251
申请日：2023-12-29
发明人： Jeffrey S. McNeil , Kishore Kumar Muchherla , Sivagnanam Parthasarathy , Patrick R. Khayat , Sundararajan Sankaranarayanan , Jeremy Binfet , Akira Goda
CPC分类号： G06F3/0659 , G06F3/0619 , G06F3/0673 , G11C16/26 , G11C16/0483
摘要： A system can include a memory device and a processing device, operatively coupled with the memory device, to perform operations including reading a first copy of data stored in a first set of memory cells comprising a first memory cell, determining whether a threshold voltage of the first memory cell is within a first range of threshold voltages, responsive to determining that the threshold voltage of the first memory cell is within the first range of threshold voltages, reading a second copy of the data stored in a second set of memory cells comprising a second memory cell, determining whether a threshold voltage of the second memory cell is within a second range of threshold voltages, and responsive to determining that the threshold voltage of the second memory cell is outside the second range, using the second copy of the data.
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公开(公告)号：US20240071435A1
公开(公告)日：2024-02-29
申请号：US18198623
申请日：2023-05-17
发明人： Phong Sy Nguyen , Patrick R. Khayat , Jeffrey S. McNeil , Dung Viet Nguyen , Kishore Kumar Muchherla , James Fitzpatrick
IPC分类号： G11C7/10
CPC分类号： G11C7/1069 , G11C7/1057 , G11C7/106
摘要： Systems and methods are disclosed including a memory device comprising a memory array and control logic, operatively coupled with the memory array. The control logic can perform operations comprising causing a read operation to be initiated with respect to a set of target cells of the memory array; obtaining, for a respective group of adjacent cells, respective cell state information; performing a set of strobe reads on the set of target cells; and generating, for a target cell of the set of target cells, semi-soft bit data based on the respective cell state information of the respective group of adjacent cells and on data obtained from a first strobe read and a second strobe read of the set of strobe reads performed on the target cell.
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公开(公告)号：US20240054046A1
公开(公告)日：2024-02-15
申请号：US17884076
申请日：2022-08-09
CPC分类号： G06F11/1044 , G11C29/08
摘要： Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising selecting a source set of memory cells of the memory device, performing a data integrity check on the source set of memory cells to obtain a data integrity metric value; responsive to determining that a data integrity metric value satisfies the threshold criterion, performing a first error-handling operation on the data stored on the source set of memory cells; responsive to determining that the first error-handling operation fails to correct the data, performing a second error-handling operation on the data; and responsive to determining that the second error-handling operation corrected the data, causing the memory device to copy the corrected data to a destination set of memory cells of the memory device.
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