公开(公告)号：US20200235112A1

公开(公告)日：2020-07-23

申请号：US16251241

申请日：2019-01-18

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Gordon A. Haller

IPC: H01L27/11556 ,  G11C5/06 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11558

Abstract: A method used in forming a memory array comprises forming a substrate comprising a conductive tier, a first insulator tier above the conductive tier, a sacrificial material tier above the first insulator tier, and a second insulator tier above the sacrificial material tier. A stack comprising vertically-alternating insulative tiers and wordline tiers is formed above the second insulator tier. Channel material is formed through the insulative tiers and the wordline tier. Horizontally-elongated trenches are formed through the stack to the sacrificial material tier. Sacrificial material is etched through the horizontally-elongated trenches selectively relative to material of the first insulator tier and selectively relative to material of the second insulator tier. A laterally-outer sidewall of the channel material is exposed in the sacrificial material tier. A conductive structure is formed directly against the laterally-outer sidewall of the channel material in the sacrificial material tier. The conductive structure extends through the first insulator tier and directly electrically couples the channel material to the conductive tier. Structure embodiments are disclosed.

公开(公告)号：US20200161332A1

公开(公告)日：2020-05-21

申请号：US16751116

申请日：2020-01-23

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Chet E. Carter ,  Collin Howder ,  John Mark Meldrim ,  Everett A. McTeer

IPC: H01L27/11582 ,  H01L21/28 ,  H01L27/11556 ,  H01L23/528 ,  H01L21/768 ,  H01L21/285 ,  H01L23/532 ,  H01L29/10 ,  H01L21/3213

Abstract: Some embodiments include a method of forming an integrated structure. An assembly is formed to include a stack of alternating first and second levels. The first levels have insulative material, and the second levels have voids which extend horizontally. The assembly includes channel material structures extending through the stack. A first metal-containing material is deposited within the voids to partially fill the voids. The deposited first metal-containing material is etched to remove some of the first metal-containing material from within the partially-filled voids. Second metal-containing material is then deposited to fill the voids.

公开(公告)号：US20200075630A1

公开(公告)日：2020-03-05

申请号：US16674823

申请日：2019-11-05

Applicant: Micron Technology, Inc.

Inventor： Changhan Kim ,  Chet E. Carter ,  Cole Smith ,  Collin Howder ,  Richard J. Hill ,  Jie Li

IPC: H01L27/11582 ,  H01L27/11529 ,  H01L27/1157 ,  H01L23/528 ,  H01L27/11568 ,  H01L29/51 ,  H01L29/49 ,  H01L21/311 ,  H01L21/02 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/788 ,  H01L29/792 ,  H01L29/66 ,  H01L29/10 ,  H01L21/28

Abstract: Some embodiments include a method of forming an assembly (e.g., a memory array). A first opening is formed through a stack of alternating first and second levels. The first levels contain silicon nitride, and the second levels contain silicon dioxide. Some of the silicon dioxide of the second levels is replaced with memory cell structures. The memory cell structures include charge-storage regions adjacent charge-blocking regions. Tunneling material is formed within the first opening, and channel material is formed adjacent the tunneling material. A second opening is formed through the stack. The second opening extends through remaining portions of the silicon dioxide, and through the silicon nitride. The remaining portions of the silicon dioxide are removed to form cavities. Conductive regions are formed within the cavities. The silicon nitride is removed to form voids between the conductive regions. Some embodiments include memory arrays.

公开(公告)号：US10283524B1

公开(公告)日：2019-05-07

申请号：US15848612

申请日：2017-12-20

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Chet E. Carter ,  Collin Howder ,  John Mark Meldrim ,  Everett A. McTeer

IPC: H01L21/28 ,  H01L29/10 ,  H01L29/49 ,  H01L21/285 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/3213 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: Some embodiments include a method of forming an integrated structure. An assembly is formed to include a stack of alternating first and second levels. The first levels have insulative material, and the second levels have voids which extend horizontally. The assembly includes channel material structures extending through the stack. A first metal-containing material is deposited within the voids to partially fill the voids. The deposited first metal-containing material is etched to remove some of the first metal-containing material from within the partially-filled voids. Second metal-containing material is then deposited to fill the voids.

公开(公告)号：US20240315027A1

公开(公告)日：2024-09-19

申请号：US18602313

申请日：2024-03-12

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Collin Howder ,  Matthew J. King

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: Memory circuitry comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises laterally-spaced memory blocks. The memory blocks individually comprise sub-blocks in an upper portion thereof. Strings of memory cells are included and that comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks. A conductive-material tier is included and that comprises conductive material in the upper portions. The conductive material extends downwardly from the conductive-material tier to below the conductive-material tier. Sub-block trenches in the upper portions are individually between immediately-laterally-adjacent of the sub-blocks and extend through the conductive-material tier. Select gates of select-gate transistors are in individual of the sub-blocks operatively alongside channel material of the select-gate transistors. The select gates comprise the conductive material of the conductive-material tier and the conductive material extending downwardly from the conductive-material tier to below the conductive-material tier alongside the channel material of the select-gate transistors. Methods are also disclosed.

公开(公告)号：US11972978B2

公开(公告)日：2024-04-30

申请号：US17736365

申请日：2022-05-04

Applicant: Micron Technology, Inc.

Inventor： Yiping Wang ,  Jordan D. Greenlee ,  Collin Howder

IPC: H10B41/10 ,  H01L21/768 ,  H01L23/522 ,  H10B41/27 ,  H10B41/30 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L21/76879 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/30 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A method used in forming a conductive via of integrated circuitry comprises forming a lining laterally over sidewalls of an elevationally-elongated opening. The lining comprises elemental-form silicon. The elemental-form silicon of an uppermost portion of the lining is ion implanted in the elevationally-elongated opening. The ion-implanted elemental-form silicon of the uppermost portion of the lining is etched selectively relative to the elemental-form silicon of a lower portion of the lining below the uppermost portion that was not subjected to said ion implanting. The elemental-form silicon of the lower portion of the lining is reacted with a metal halide to form elemental-form metal in a lower portion of the elevationally-elongated opening that is the metal from the metal halide. Conductive material in the elevationally-elongated opening is formed atop and directly against the elemental-form metal. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20240113012A1

公开(公告)日：2024-04-04

申请号：US17937360

申请日：2022-09-30

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Yiping Wang

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/5226 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76814 ,  H01L23/53295 ,  H01L27/11556 ,  H01L27/11582

Abstract: A microelectronic device comprises a stack structure, a staircase structure, a first liner material, a liner structure, conductive contact structures, and barrier structures. The stack structure comprises vertically alternating conductive structures and insulative structures arranged in tiers. Each of the tiers individually comprises one of the conductive structures and one of the insulative structures. The staircase structure has steps comprising edges of at least some of the tiers of the stack structure. The first liner material is on the steps of the staircase structure, and the liner structure on the first liner material. The conductive contact structures extend through the first liner material and the liner structure and to the conductive structures of the stack structure. The barrier structures are between the conductive contact structures and the liner structure vertically span substantially the same tiers of the stack structure as the liner structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US20240047362A1

公开(公告)日：2024-02-08

申请号：US17881308

申请日：2022-08-04

Applicant: Micron Technology, Inc.

Inventor： Yiping Wang ,  Jiewei Chen ,  Collin Howder

IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/535 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack extends from a memory-array region into a stair-step region. The stair-step region comprises a cavity comprising a flight of stairs. The first tiers are conductive and the second tiers are insulative at least in a finished-circuitry construction. A lining is formed in and that less-than-fills the cavity atop treads of the stairs. Individual of the treads comprise conducting material of one of the first tiers in the finished-circuitry construction. The lining that is atop the treads is replaced with at least one of metal material, polysilicon, or SiGe and insulative material is provided in remaining volume of the cavity directly above the at least one of the metal material, the polysilicon, or the SiGe. Conductive vias are formed through the insulative material and the at least one of the metal material, the polysilicon, or the SiGe. Individual of the conductive vias are directly above and directly against the conducting material of one of the individual treads. Other embodiments, including structure, are disclosed.

公开(公告)号：US20230284451A1

公开(公告)日：2023-09-07

申请号：US18140516

申请日：2023-04-27

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Gordon A. Haller

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: Some embodiments include an integrated structure having a stack of memory cell levels. A pair of channel-material-pillars extend through the stack. A source structure is under the stack. The source structure includes a portion having an upper region, a lower region, and an intermediate region between the upper and lower regions. The upper and lower regions have a same composition and join to one another at edge locations. The intermediate region has a different composition than the upper and lower regions. The edge locations are directly against the channel material of the channel-material-pillars. Some embodiments include methods of forming an integrated assembly.

公开(公告)号：US11678483B2

公开(公告)日：2023-06-13

申请号：US17160956

申请日：2021-01-28

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Chris M. Carlson ,  Collin Howder

IPC: H01L27/11556 ,  H10B41/27 ,  G11C8/14 ,  G11C16/04 ,  G06F3/06 ,  H10B41/35 ,  H10B41/41 ,  H10B41/60 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B41/27 ,  G06F3/0688 ,  G11C8/14 ,  G11C16/0466 ,  H10B41/35 ,  H10B41/41 ,  H10B41/60 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. First charge-blocking material is formed to extend elevationally along the vertically-alternating tiers. The first charge-blocking material has k of at least 7.0 and comprises a metal oxide. A second charge-blocking material is formed laterally inward of the first charge-blocking material. The second charge-blocking material has k less than 7.0. Storage material is formed laterally inward of the second charge-blocking material. Insulative charge-passage material is formed laterally inward of the storage material. Channel material is formed to extend elevationally along the insulative tiers and the wordline tiers laterally inward of the insulative charge-passage material. Structure embodiments are disclosed.