公开(公告)号：US20080049323A1

公开(公告)日：2008-02-28

申请号：US11878766

申请日：2007-07-26

申请人： Susumu Sugiyama ,  Kunihiro Atsumi ,  Hajime Nakayama

发明人： Susumu Sugiyama ,  Kunihiro Atsumi ,  Hajime Nakayama

IPC分类号： G02B5/30 ,  B29D11/00 ,  G02F1/1335

CPC分类号： G02B5/3083 ,  B29D11/0074 ,  G02F1/13363 ,  Y10T428/1041

摘要： An optical film includes at least one kind of humidity dependency improver that improves ΔRe, wherein the optical film has a ratio of Re/Rth which is larger as a wavelength is longer in the visible wavelength region; and Re which is larger as a wavelength is longer in the visible wavelength region, wherein Re represents an in-plane retardation (unit: nm) of the optical film; Rth represents a retardation (unit: nm) in a thickness direction of the optical film; and ΔRe represents a humidity dependency of Re defined by the following formula (1): ΔRe=|Re(550)10%RH−Re(550)80%RH|,:   Formula (1) wherein Re(550)10%RH represents Re at a wavelength of 550 nm, at a temperature of 25° C. and at a relative humidity of 10%; and Re(550)80%RH represents Re at a wavelength of 550 nm, at a temperature of 25° C. and at a relative humidity of 80%.

摘要翻译： 一种光学膜包括至少一种改善DeltaRe的湿度依赖性改进剂，其中该光学膜具有在可见波长区域中波长较长的Re / Rth比; 并且在可见光波长区域中作为波长较大的Re较大，其中Re表示光学膜的面内延迟（单位：nm）; Rth表示光学膜的厚度方向的延迟（单位：nm） DeltaRe表示由以下公式（1）定义的Re的湿度依赖性：<？in-line-formula description =“In-line Formulas”end =“lead”？> DeltaRe = | Re（550）10％ Re（550）80％RH |，：式（1）<？in-line-formula description =“In-line formula”end =“tail”？>其中Re（550）10％RH表示波长为 550nm，温度25℃，相对湿度10％; Re（550）80％RH表示在波长550nm，温度25℃，相对湿度80％的Re。

公开(公告)号：US06737709B1

公开(公告)日：2004-05-18

申请号：US09210540

申请日：1998-12-14

申请人： Hajime Nakayama

发明人： Hajime Nakayama

IPC分类号： H01L2976

CPC分类号： H01L21/823842 ,  H01L21/823871

摘要： A semiconductor device suppressing the lateral diffusion of impurities doped in a PMOS and NMOS and shortening the distance between the PMOS and NMOS to reduce the size of the semiconductor device, including PMOS and NMOS formation regions isolated by an element isolation region; a p-type gate electrode arranged on the PMOS formation region; an n-type gate electrode arranged on the NMOS formation region; and first and second impurity storage regions arranged in a direction different from that of the arrangement of the p-type and n-type gate electrodes. An end of the first impurity storage region is connected to the p-type gate electrode, an end of the second impurity storage region is connected to the n-type gate electrode, and the other ends of the first and second impurity storage regions are electrically connected.

摘要翻译： 一种抑制掺杂在PMOS和NMOS中的杂质的横向扩散的半导体器件，并且缩短了PMOS和NMOS之间的距离，以减小半导体器件的尺寸，包括由元件隔离区隔离的PMOS和NMOS形成区域; 配置在PMOS形成区域上的p型栅电极; 配置在NMOS形成区域上的n型栅电极; 以及第一和第二杂质存储区域，其布置方向与p型和n型栅电极的布置方向不同。 第一杂质储存区的一端连接到p型栅电极，第二杂质储存区的一端与n型栅电极连接，第一和第二杂质储存区的另一端电 连接的。

公开(公告)号：US06568073B1

公开(公告)日：2003-05-27

申请号：US09036494

申请日：1998-03-06

申请人： Naoki Fukutomi ,  Hidehiro Nakamura ,  Hajime Nakayama ,  Yoshiaki Tsubomatsu ,  Masanori Nakamura ,  Kouichi Kaitou ,  Atsushi Kuwano ,  Itsuo Watanabe ,  Masahiko Itabashi

发明人： Naoki Fukutomi ,  Hidehiro Nakamura ,  Hajime Nakayama ,  Yoshiaki Tsubomatsu ,  Masanori Nakamura ,  Kouichi Kaitou ,  Atsushi Kuwano ,  Itsuo Watanabe ,  Masahiko Itabashi

IPC分类号： H05K310

CPC分类号： H05K3/4658 ,  G01R1/07314 ,  H05K3/062 ,  H05K3/205 ,  H05K3/4007 ,  H05K3/428 ,  H05K3/4647 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0367 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/09781 ,  H05K2203/0152 ,  H05K2203/025 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0726 ,  H05K2203/0733 ,  H05K2203/1476 ,  Y10S29/016 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49158

摘要： The present invention provides a process for the fabrication of a wiring board, which comprises the following steps: (a) forming a first wiring pattern on a first side of a self-supporting carrier metal foil so as to obtain a self-supporting wiring sheet comprising the carrier metal foil and the first wiring pattern; (b) superposing and pressing the first side of said self-supporting wiring sheet on and against an insulating substrate so that the first wiring pattern is_embedded in the insulating substrate and constitutes a surface with the insulating substrate; and (c) etching off desired portions of said carrier metal foil to form a second wiring pattern made of said carrier metal foil remaining on the surface constituted by the insulating substrate and the first wiring pattern. The present invention also provides the wiring board for electrical tests so fabricated.

摘要翻译： 本发明提供一种制造布线板的方法，其包括以下步骤：（a）在自支撑载体金属箔的第一面上形成第一布线图案，以获得自支撑布线板 包括载体金属箔和第一布线图案; （b）将所述自支撑布线板的第一侧叠置并压在绝缘基板上，使得第一布线图案嵌入在绝缘基板中并与绝缘基板构成表面; 和（c）蚀刻所述载体金属箔的期望部分，以形成由保留在由绝缘基板和第一布线图案构成的表面上的所述载体金属箔制成的第二布线图案。 本发明还提供了如此制造的用于电测试的接线板。

公开(公告)号：US06452274B1

公开(公告)日：2002-09-17

申请号：US09192335

申请日：1998-11-16

申请人： Toshiaki Hasegawa ,  Hajime Nakayama

发明人： Toshiaki Hasegawa ,  Hajime Nakayama

IPC分类号： H01L5140

CPC分类号： H01L21/76802 ,  H01L21/02115 ,  H01L21/0212 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/3127 ,  H01L21/76801 ,  H01L21/76835 ,  H01L21/76885 ,  H01L23/3677 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A semiconductor device including a semiconductor substrate, an insulating layer formed on the substrate, a dielectric organic layer formed on the insulating layer and having a dielectric constant of not more than 3.0, and an interconnection layer in contact with the insulating layer in the dielectric organic layer, wherein the upper surface of the interconnection layer is formed higher than the upper surface of the dielectric organic layer, and a method of manufacture thereof.

摘要翻译： 一种半导体器件，包括半导体衬底，形成在衬底上的绝缘层，形成在绝缘层上并具有不大于3.0的介电常数的介电有机层以及与介电有机物中的绝缘层接触的互连层 层，其中互连层的上表面形成为高于介电有机层的上表面，及其制造方法。

公开(公告)号：US5891285A

公开(公告)日：1999-04-06

申请号：US853106

申请日：1997-05-08

申请人： Hajime Nakayama

发明人： Hajime Nakayama

IPC分类号： C25D1/00

CPC分类号： C25D1/003

摘要： A process for manufacturing electroformed patterns includes the following steps: forming electroformed closed line graphic patterns and an electroformed line surrounding said patterns (optionally together with an electroformed island) on a surface of a conductive substrate; peeling the electroformed patterns and the electroformed line (optionally together with the electroformed island) from the conductive substrate to transfer them onto a pressure-sensitive adhesive layer provided on a support; injecting or printing a coating material inside the closed line graphic electroformed patterns and converting the coating material to coating films; forming a firmly bonding adhesive layer on a whole surface of the support on its side where the electroformed patterns, the coating films and the electroformed line (optionally together with the electroformed island) are retained; removing the electroformed line (optionally together with the electroformed island); separating the electroformed patterns and the coating films from the support and, simultaneously therewith, adhering the electroformed patterns and coating films through the firmly bonding adhesive layer onto a surface of an adherend. This process enables simple formation of electroformed patterns provided with coating films which may be a luminous paint, and is suitable for making a timepiece face.

摘要翻译： 制造电铸图案的方法包括以下步骤：在导电基材的表面上形成电铸闭合线图形和围绕所述图案（可选地与电铸岛一起）的电铸线; 将电铸图案和电铸线（可选地与电铸岛一起）从导电基材剥离，将其转印到设置在载体上的压敏粘合剂层上; 在封闭线图形电铸图案内注入或印刷涂料，并将涂料转化成涂膜; 在支撑体的整个表面上形成牢固粘合的粘合剂层，其中电铸图案，涂膜和电铸线（可选地与电铸岛一起）被保留; 去除电铸线（可选地与电铸岛一起）; 将电铸图案和涂膜从支撑体分离，同时将电铸图案和涂膜通过牢固粘合的粘合剂层粘附到被粘物的表面上。 该方法能够简单地形成具有可以是发光漆的涂膜的电铸图案，并且适于制造钟表面。