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    SIDEWALL SEMICONDUCTOR TRANSISTORS
    62.
    发明申请
    SIDEWALL SEMICONDUCTOR TRANSISTORS 有权
    端子半导体晶体管

    公开(公告)号：US20080286909A1

    公开(公告)日：2008-11-20

    申请号：US11867840

    申请日：2007-10-05

    申请人： Huilong Zhu ,  Lawrence A. Clevenger ,  Omer H. Dokumaci ,  Kaushik A. Kumar ,  Carl J. Radens ,  Dureseti Chidambarrao

    发明人： Huilong Zhu ,  Lawrence A. Clevenger ,  Omer H. Dokumaci ,  Kaushik A. Kumar ,  Carl J. Radens ,  Dureseti Chidambarrao

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/1083 ,  H01L29/66795

    摘要： A novel transistor structure and method for fabricating the same. First, a substrate, a semiconductor region, a gate dielectric region, and a gate block are provided. The semiconductor region, the gate dielectric region, and the gate block are on the substrate. The gate dielectric region is sandwiched between the semiconductor region and the gate block. The semiconductor region is electrically insulated from the gate block by the gate dielectric region. The semiconductor region and the gate dielectric region share an interface surface which is essentially perpendicular to a top surface of the substrate. The semiconductor region and the gate dielectric region do not share any interface surface that is essentially parallel to a top surface of the substrate. Next, a gate region is formed from the gate block. Then, first and second source/drain regions are formed in the semiconductor region.

    摘要翻译： 一种新颖的晶体管结构及其制造方法。 首先，提供衬底，半导体区域，栅极介质区域和栅极块。 半导体区域，栅极电介质区域和栅极块在衬底上。 栅极电介质区域夹在半导体区域和栅极块之间。 半导体区域通过栅极电介质区域与栅极块电绝缘。 半导体区域和栅极电介质区域共享基本上垂直于衬底顶表面的界面。 半导体区域和栅极介电区域不共享基本上平行于衬底顶表面的任何界面表面。 接下来，从栅极块形成栅极区域。 然后，在半导体区域中形成第一和第二源极/漏极区域。

    Method for reduced N+ diffusion in strained Si on SiGe substrate
    63.
    发明授权
    Method for reduced N+ diffusion in strained Si on SiGe substrate 失效
    SiGe衬底上应变Si中N +扩散减少的方法

    公开(公告)号：US07297601B2

    公开(公告)日：2007-11-20

    申请号：US11283882

    申请日：2005-11-22

    申请人： Dureseti Chidambarrao ,  Omer H. Dokumaci

    发明人： Dureseti Chidambarrao ,  Omer H. Dokumaci

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/1054 ,  H01L29/6656

    摘要： Method for manufacturing a semiconductor device. The method includes forming source and drain extension regions in an upper surface of a SiGe-based substrate. The source and drain extension regions contain an N type impurity. Reducing vacancy concentration in the source and drain extension regions to decrease diffusion of the N type impurity contained in the first source and drain extension regions.

    摘要翻译： 半导体器件的制造方法 该方法包括在基于SiGe的衬底的上表面中形成源极和漏极延伸区域。 源极和漏极延伸区域包含N型杂质。 降低源极和漏极延伸区域中的空位浓度，以减少第一源极和漏极延伸区域中包含的N型杂质的扩散。

    Strained Si on multiple materials for bulk or SOI substrates
    65.
    发明授权
    Strained Si on multiple materials for bulk or SOI substrates 有权
    应变Si在多种材料上用于体或SOI衬底

    公开(公告)号：US07223994B2

    公开(公告)日：2007-05-29

    申请号：US10859736

    申请日：2004-06-03

    申请人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Oleg G. Gluschenkov ,  Huilong Zhu

    发明人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Oleg G. Gluschenkov ,  Huilong Zhu

    IPC分类号： H01L29/06 ,  H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L21/0336

    CPC分类号： H01L29/78 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054

    摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate, a first layered stack atop the substrate, the first layered stack comprising a first Si-containing portion of the substrate, a compressive layer atop the Si-containing portion of the substrate, and a semiconducting silicon layer atop the compressive layer; and a second layered stack atop the substrate, the second layered stack comprising a second-silicon containing layer portion of the substrate, a tensile layer atop the second Si-containing portion of the substrate, and a second semiconducting silicon-layer atop the tensile layer.

    摘要翻译： 本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。 广义上，应变Si结构包括衬底，在衬底顶部的第一层叠堆叠，第一层叠堆叠包括衬底的第一含Si部分，衬底的含Si部分顶部的压缩层和半导体硅 层在压缩层顶上; 以及在所述衬底顶部的第二层叠叠层，所述第二层叠堆叠包括所述衬底的第二硅含有层部分，在所述衬底的所述第二含Si部分顶部的拉伸层，以及在所述拉伸层顶部的第二半导体硅层 。

    High performance logic and high density embedded dram with borderless contact and antispacer
    66.
    发明授权
    High performance logic and high density embedded dram with borderless contact and antispacer 失效
    高性能逻辑和高密度嵌入式电脑，无边界接触和对抗

    公开(公告)号：US06873010B2

    公开(公告)日：2005-03-29

    申请号：US10682430

    申请日：2003-10-10

    申请人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Bruce Bennett Doris ,  Oleg Gluschenkov ,  Rajarao Jammy ,  Jack Allen Mandelman

    发明人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Bruce Bennett Doris ,  Oleg Gluschenkov ,  Rajarao Jammy ,  Jack Allen Mandelman

    IPC分类号： H01L21/8242 ,  H01L29/76

    CPC分类号： H01L27/10876 ,  H01L27/10864 ,  H01L27/10891 ,  H01L27/10894

    摘要： An integrated circuit includes memory cells having array transistors separated by minimum lithographic feature and unsilicided metal bit lines encapsulated by a diffusion barrier while high performance logic transistors may be formed on the same chip without compromise of performance including an effective channel, silicided contacts for low source/drain contact resistance, extension and halo implants for control of short channel effects and a dual work function semiconductor gate having a high impurity concentration and correspondingly thin depletion layer thickness commensurate with state of the art gate dielectric thickness. This structure is achieved by development of thick/tall structures of differing materials using a mask or anti-spacer, preferably of an easily planarized material, and using a similar mask planarized to the height of the structures of differing materials to decouple substrate and gate implantations in the logic transistors.

    摘要翻译： 集成电路包括具有由最小光刻特征分隔的阵列晶体管和由扩散阻挡层封装的非硅化金属位线的存储单元，而高性能逻辑晶体管可以形成在同一芯片上而不损害包括有效通道在内的性能， /漏极接触电阻，用于控制短沟道效应的延伸和晕轮植入物以及与现有技术的栅介质厚度相当的具有高杂质浓度和相应薄的耗尽层厚度的双功函数半导体栅极。 该结构通过使用掩模或抗间隔物（优选易于平坦化的材料）开发不同材料的厚/高结构来实现，并且使用平坦化为不同材料的结构的高度的类似掩模以使基板和栅极注入分离 在逻辑晶体管中。

    Ultra-shallow junction dopant layer having a peak concentration within a dielectric layer
    67.
    发明授权
    Ultra-shallow junction dopant layer having a peak concentration within a dielectric layer 失效
    在介电层内具有峰值浓度的超浅结掺杂剂层

    公开(公告)号：US06329704B1

    公开(公告)日：2001-12-11

    申请号：US09458530

    申请日：1999-12-09

    申请人： Hiroyuki Akatsu ,  Omer H. Dokumaci ,  Suryanarayan G. Hegde ,  Yujun Li ,  Rajesh Rengarajan ,  Paul A. Ronsheim

    发明人： Hiroyuki Akatsu ,  Omer H. Dokumaci ,  Suryanarayan G. Hegde ,  Yujun Li ,  Rajesh Rengarajan ,  Paul A. Ronsheim

    IPC分类号： H01L29167

    CPC分类号： H01L21/2652 ,  H01L21/2254 ,  H01L21/2255 ,  H01L29/6659

    摘要： A process for forming an ultra-shallow junction depth, doped region within a silicon substrate. The process includes forming a dielectric film on the substrate, then implanting an ionic dopant species into the structure. The profile of the implanted species includes a population implanted through the dielectric film and into the silicon substrate, and a peak concentration deliberately confined in the dielectric film in close proximity to the interface between the dielectric film and the silicon substrate. A high-energy, low-dosage implant process is used and produces a structure that is substantially free of dislocation loops and other defect clusters. An annealing process is used to drive the peak concentration closer to the interface, and some of the population of the originally implanted species from the dielectric film into the silicon substrate. A low thermal budget is maintained because of the proximity of the as-implanted peak concentration to the interface and the presence of species implanted through the dielectric film and into the substrate.

    摘要翻译： 一种用于在硅衬底内形成超浅结深度掺杂区的工艺。 该方法包括在衬底上形成电介质膜，然后将离子掺杂剂物质注入结构中。 植入物种的轮廓包括通过电介质膜注入硅衬底中的群体，以及刻意限制在电介质膜中的接近于介电膜和硅衬底之间界面的峰值浓度。 使用高能量，低剂量的植入工艺，并且产生基本上不含位错环和其它缺陷簇的结构。 使用退火工艺来驱动更接近界面的峰值浓度，以及从电介质膜到硅衬底的最初注入物质的一些群体。 由于植入的峰浓度与界面的接近以及通过电介质膜注入并进入衬底的物质的存在，维持了低热量预算。

    FinFETs single-sided implant formation
    70.
    发明授权
    FinFETs single-sided implant formation 有权
    FinFET单面植入物形成

    公开(公告)号：US07994612B2

    公开(公告)日：2011-08-09

    申请号：US12106476

    申请日：2008-04-21

    申请人： Brent A. Anderson ,  Andres Bryant ,  Josephine B. Chang ,  Omer H. Dokumaci ,  Edward J. Nowak

    发明人： Brent A. Anderson ,  Andres Bryant ,  Josephine B. Chang ,  Omer H. Dokumaci ,  Edward J. Nowak

    IPC分类号： H01L21/02

    CPC分类号： H01L21/26513 ,  H01L21/26586 ,  H01L29/66803 ,  H01L29/785

    摘要： A method patterns pairs of semiconducting fins on an insulator layer and then patterns a linear gate conductor structure over and perpendicular to the fins. Next, the method patterns a mask on the insulator layer adjacent the fins such that sidewalls of the mask are parallel to the fins and are spaced from the fins a predetermined distance. The method performs an angled impurity implant into regions of the fins not protected by the gate conductor structure and the mask. This process forms impurity concentrations within the fins that are asymmetric and that mirror one another in adjacent pairs of fins.

    摘要翻译： 一种方法在绝缘体层上形成一对半导体翅片，然后在鳍片上并垂直于翅片形成线性栅极导体结构。 接下来，该方法在与鳍片相邻的绝缘体层上形成掩模，使得掩模的侧壁平行于翅片并与翅片间隔预定距离。 该方法对未被栅极导体结构和掩模保护的鳍片的区域进行倾斜的杂质注入。 该方法在翅片内形成不对称的杂质浓度，并且在相邻的翅片对中彼此相互镜像。