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公开(公告)号：US20130065393A1
公开(公告)日：2013-03-14
申请号：US13229912
申请日：2011-09-12
IPC分类号： H01L21/768
CPC分类号： H01L21/3081 , H01L21/76898
摘要： A method for forming a through silicon via (TSV) in a substrate may include forming a dielectric layer on the substrate; forming an opening through the dielectric layer and into the substrate using a single mask over the dielectric layer; expanding the opening in the dielectric layer, undercutting the single mask, to form an expanded upper portion; removing the single mask; and filling the opening, including the expanded upper portion, with a conductor. A resulting structure may include a substrate; a dielectric layer over the substrate; and a self-aligned through silicon via (TSV) extending through the dielectric layer and the substrate.
摘要翻译： 在衬底中形成贯穿硅通孔（TSV）的方法可以包括在衬底上形成电介质层; 通过所述电介质层形成开口并使用所述电介质层上的单个掩模进入所述衬底; 使介电层中的开口膨胀，对单个掩模进行底切以形成膨胀的上部; 去除单个面具; 并且用导体填充包括扩大的上部的开口。 所得到的结构可以包括基底; 介电层; 以及延伸穿过电介质层和衬底的自对准通过硅通孔（TSV）。
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62.发明申请Design Structure, Methods, and Apparatus Involving Photoconductor-on-Active Pixel Devices 有权涉及光电导体活性像素器件的设计结构，方法和设备公开(公告)号：US20120146115A1
公开(公告)日：2012-06-14
申请号：US12967625
申请日：2010-12-14
IPC分类号： H01L31/112 , G06F17/50
CPC分类号： H01L31/105 , H01L27/14632 , H01L27/14636 , H01L27/14665 , H01L27/14687
摘要： A design structure embodied in a machine readable medium used in a design process includes a first dielectric layer disposed on an intermediary layer, a first conductive pad portion and a first interconnect portion disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer, a first capping layer disposed on the first interconnect portion and a portion of the first conductive pad portion, a second capping layer disposed on the first capping layer and a portion of the second dielectric layer, an n-type doped silicon layer disposed on the second capping layer and the first conductive pad portion, an intrinsic silicon layer disposed on the n-type doped silicon layer, and a p-type doped silicon layer disposed on the intrinsic silicon layer.
摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构包括设置在中间层上的第一介电层，设置在第一介电层上的第一导电焊盘部分和第一互连部分，设置在第一介电层上的第二介电层 电介质层，设置在第一互连部分上的第一覆盖层和第一导电焊盘部分的一部分，设置在第一覆盖层上的第二封盖层和第二介电层的一部分，设置n型掺杂硅层 在第二覆盖层和第一导电焊盘部分上，设置在n型掺杂硅层上的本征硅层和设置在本征硅层上的p型掺杂硅层。
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公开(公告)号：US08168474B1
公开(公告)日：2012-05-01
申请号：US12987402
申请日：2011-01-10
申请人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Yen L. Lim
发明人： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Yen L. Lim
IPC分类号： H01L21/00
CPC分类号： H01L21/78 , H01L21/76898
摘要： Systems and methods simultaneously form first openings and second openings in a substrate. The first openings are formed smaller than the second openings. The method also simultaneously forms a first material in the first openings and the second openings. The first material fills the first openings, and the first material lines the second openings. The method forms a second material different than the first material in the second openings. The second material fills the second openings. The method forms a plurality of integrated circuit structures over the first material and the second material within the second openings. The method applies mechanical stress to the substrate to cause the substrate to split along the first openings.
摘要翻译： 系统和方法同时在衬底中形成第一开口和第二开口。 第一开口形成为小于第二开口。 该方法还同时在第一开口和第二开口中形成第一材料。 第一材料填充第一开口，第一材料将第二开口排列。 该方法形成与第二开口中的第一材料不同的第二材料。 第二材料填充第二开口。 该方法在第二开口内的第一材料和第二材料上形成多个集成电路结构。 该方法对基板施加机械应力以使基板沿着第一开口分开。
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64.发明授权Systems for real-time contamination, environmental, or physical monitoring of a photomask 有权用于光掩模的实时污染，环境或物理监测的系统公开(公告)号：US08136055B2
公开(公告)日：2012-03-13
申请号：US12182672
申请日：2008-07-30
IPC分类号： G06F17/50
CPC分类号： G03F7/70916 , G03F7/70525 , G03F7/70741 , G03F7/7085 , G03F7/70991
摘要： Systems for real-time contamination, environmental, or physical monitoring of a photomask. The system includes an electronics package physically mounted to the photomask and a processing device in communication with the electronics package. The electronics package includes a sensor configured to monitor the attribute and generate sensor data. The processing device is configured to analyze the sensor data communicated from the electronics package to the processing device.
摘要翻译： 用于光掩模的实时污染，环境或物理监测的系统。 该系统包括物理地安装到光掩模的电子封装以及与电子封装通信的处理装置。 电子组件包括配置成监视属性并生成传感器数据的传感器。 处理装置被配置为分析从电子包装传送到处理装置的传感器数据。
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65.发明授权IC chip and design structure including stitched circuitry region boundary identification 有权IC芯片和设计结构包括缝合电路区域边界识别公开(公告)号：US08006211B2
公开(公告)日：2011-08-23
申请号：US12112336
申请日：2008-04-30
IPC分类号： G06F17/50
CPC分类号： G03F7/70475 , G03F1/00 , G03F1/50 , G03F7/70466
摘要： Stitched circuitry region boundary identification for a stitched IC chip layout is presented along with a related IC chip and design structure. One method includes obtaining a circuit design for an integrated circuit (IC) chip layout that exceeds a size of a photolithography tool field, wherein the IC chip layout includes a stitched circuitry region; and modifying the IC chip layout to include a boundary identification identifying a boundary of the stitched circuitry region at which stitching occurs, wherein the boundary identification takes the form of a negative space in the IC chip layout. One IC chip may include a plurality of stitched circuitry regions; and a boundary identification identifying a boundary between a pair of the stitched circuitry regions, wherein the boundary identification takes the form of a negative space in a layer of the IC chip.
摘要翻译： 针对IC芯片布线的缝合电路区域边界识别以及相关的IC芯片和设计结构。 一种方法包括获得超过光刻工具领域的尺寸的集成电路（IC）芯片布局的电路设计，其中IC芯片布局包括缝合电路区域; 以及修改IC芯片布局以包括标识发生缝合的缝合电路区域的边界的边界标识，其中边界识别在IC芯片布局中采取负空间的形式。 一个IC芯片可以包括多个缝合电路区域; 以及识别一对缝合电路区域之间的边界的边界识别，其中边界识别在IC芯片的层中采取负空间的形式。
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公开(公告)号：US08003428B2
公开(公告)日：2011-08-23
申请号：US12056736
申请日：2008-03-27
IPC分类号： H01L21/00
CPC分类号： H01L27/14627 , H01L27/14609 , H01L27/14621 , H01L27/14685
摘要： A flat-top convex-bottom lower lens is formed by first applying a positive tone photoresist over a silicon oxide layer and an optional metallic barrier layer thereupon in a back-end-of-line (BEOL) metallization structure. The positive tone photoresist is exposed under defocused illumination conditions and/or employing a half-tone mask so that a cross-sectional profile of the positive tone photoresist after exposure contains a continuous and smooth concave profile, which is transferred into the underlying silicon oxide layer to form a concave cavity therein. After removing the photoresist, the cavity is filled with a high refractive index material such as silicon nitride, and planarized to form a flat-top convex-bottom lower lens. Various aluminum metal structures, a color filter, and a convex-top flat-bottom upper lens are thereafter formed so that the upper lens and the lower lens constitute a composite lens system.
摘要翻译： 通过在后端行（BEOL）金属化结构中首先在氧化硅层上施加正色调光致抗蚀剂和可选的金属阻挡层来形成平顶凸底底部透镜。 正色调光致抗蚀剂在散焦照明条件下和/或使用半色调掩模下曝光，使得曝光后的正色调光致抗蚀剂的横截面轮廓包含连续且平滑的凹形轮廓，其被转移到下面的氧化硅层 以在其中形成凹腔。 在除去光致抗蚀剂之后，用诸如氮化硅的高折射率材料填充空腔，并且平坦化以形成平顶凸底底部下透镜。 此后形成各种铝金属结构，滤色器和凸顶平底上透镜，使得上透镜和下透镜构成复合透镜系统。
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67.发明授权Stitched circuitry region boundary identification for stitched IC chip layout 有权缝合IC芯片布局的缝合电路区域边界识别公开(公告)号：US07958482B2
公开(公告)日：2011-06-07
申请号：US12112329
申请日：2008-04-30
IPC分类号： G06F17/50
CPC分类号： G03F7/70475
摘要： Stitched circuitry region boundary identification for a stitched IC chip layout is presented along with a related IC chip and design structure. One method includes obtaining a circuit design for an integrated circuit (IC) chip layout that exceeds a size of a photolithography tool field, wherein the IC chip layout includes a stitched circuitry region; and modifying the IC chip layout to include a boundary identification identifying a boundary of the stitched circuitry region at which stitching occurs, wherein the boundary identification takes the form of a negative space in the IC chip layout. One IC chip may include a plurality of stitched circuitry regions; and a boundary identification identifying a boundary between a pair of the stitched circuitry regions, wherein the boundary identification takes the form of a negative space in a layer of the IC chip.
摘要翻译： 针对IC芯片布线的缝合电路区域边界识别以及相关的IC芯片和设计结构。 一种方法包括获得超过光刻工具领域的尺寸的集成电路（IC）芯片布局的电路设计，其中IC芯片布局包括缝合电路区域; 以及修改IC芯片布局以包括标识发生缝合的缝合电路区域的边界的边界标识，其中边界识别在IC芯片布局中采取负空间的形式。 一个IC芯片可以包括多个缝合电路区域; 以及识别一对缝合电路区域之间的边界的边界识别，其中边界识别在IC芯片的层中采取负空间的形式。
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公开(公告)号：US20090242948A1
公开(公告)日：2009-10-01
申请号：US12056736
申请日：2008-03-27
IPC分类号： H01L31/0232 , H01L31/18
CPC分类号： H01L27/14627 , H01L27/14609 , H01L27/14621 , H01L27/14685
摘要： A flat-top convex-bottom lower lens is formed by first applying a positive tone photoresist over a silicon oxide layer and an optional metallic barrier layer thereupon in a back-end-of-line (BEOL) metallization structure. The positive tone photoresist is exposed under defocused illumination conditions and/or employing a half-tone mask so that a cross-sectional profile of the positive tone photoresist after exposure contains a continuous and smooth concave profile, which is transferred into the underlying silicon oxide layer to form a concave cavity therein. After removing the photoresist, the cavity is filled with a high refractive index material such as silicon nitride, and planarized to form a flat-top convex-bottom lower lens. Various aluminum metal structures, a color filter, and a convex-top flat-bottom upper lens are thereafter formed so that the upper lens and the lower lens constitute a composite lens system.
摘要翻译： 通过在后端行（BEOL）金属化结构中首先在氧化硅层上施加正色调光致抗蚀剂和可选的金属阻挡层来形成平顶凸底底部透镜。 正色调光致抗蚀剂在散焦照明条件下和/或使用半色调掩模下曝光，使得曝光后的正色调光致抗蚀剂的横截面轮廓包含连续且平滑的凹形轮廓，其被转移到下面的氧化硅层 以在其中形成凹腔。 在除去光致抗蚀剂之后，用诸如氮化硅的高折射率材料填充空腔，并且平坦化以形成平顶凸底底部下透镜。 此后形成各种铝金属结构，滤色器和凸顶平底上透镜，使得上透镜和下透镜构成复合透镜系统。
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公开(公告)号：US20080209382A1
公开(公告)日：2008-08-28
申请号：US11849461
申请日：2007-09-04
申请人： Timothy G. Dunham , Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Valarmathi C. Shanmugam
发明人： Timothy G. Dunham , Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Valarmathi C. Shanmugam
IPC分类号： G06F17/50
CPC分类号： G03F7/70475 , G03F7/70466 , G03F7/70691
摘要： Stitched integrated circuit (IC) chip layout design structures are disclosed. In one embodiment, a design structure embodied in a machine readable medium used in a design process includes: an integrated circuit (IC) chip exceeding a size of a photolithography tool field, the IC chip layout including: a plurality of stitched regions including at least one redundant stitched region or at least one unique stitched region; and for each stitched region: a boundary identification identifying a boundary of the stitched region at which stitching occurs.
摘要翻译： 公开了拼接集成电路（IC）芯片布局设计结构。 在一个实施例中，体现在设计过程中使用的机器可读介质中的设计结构包括：超过光刻工具领域尺寸的集成电路（IC）芯片，所述IC芯片布局包括：至少包括多个缝合区域 一个冗余缝合区域或至少一个独特的缝合区域; 并且针对每个缝合区域：识别发生缝合的缝合区域的边界的边界标识。
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公开(公告)号：US20080116537A1
公开(公告)日：2008-05-22
申请号：US11560882
申请日：2006-11-17
申请人： James W. Adkisson , Jeffrey P. Gambino , Zhong-Xiang He , Mark D. Jaffe , Robert K. Leidy , Stephen E. Luce , Richard J. Rassel , Edmund J. Sprogis
发明人： James W. Adkisson , Jeffrey P. Gambino , Zhong-Xiang He , Mark D. Jaffe , Robert K. Leidy , Stephen E. Luce , Richard J. Rassel , Edmund J. Sprogis
IPC分类号： H01L27/146 , H01L21/04
CPC分类号： H01L27/14687 , H01L27/14618 , H01L27/14621 , H01L27/14627 , H01L27/14632 , H01L27/14685 , H01L2224/05001 , H01L2224/05008 , H01L2224/05124 , H01L2224/05548 , H01L2224/05569 , H01L2224/05647 , H01L2224/13 , H01L2924/00014
摘要： A CMOS image sensor array and method of fabrication. The CMOS imager sensor array comprises a substrate; an array of light receiving pixel structures formed above the substrate, the array having formed therein “m” levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer; a dense logic wiring region formed adjacent to the array of light receiving pixel structures having “n” levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer, where n>m. A microlens array having microlenses and color filters formed above the interlevel dielectric material layer, a microlens and respective color filter in alignment with a respective light receiving structure formed at a surface of the substrate. A top surface of the interlevel dielectric material layer beneath the microlens array is recessed from a top surface of the interlevel dielectric material layers of the dense logic wiring region.
摘要翻译： CMOS图像传感器阵列及其制造方法。 CMOS成像器传感器阵列包括衬底; 形成在衬底上方的光接收像素结构的阵列，阵列中形成有“m”级的导电结构，每个级形成在相应的层间介电材料层中; 与具有“n”级的导电结构的光接收像素结构的阵列相邻形成的密集的逻辑布线区域，每个层级形成在相应的层间电介质材料层中，其中n> m。 具有形成在层间电介质材料层上方的微透镜和滤色器的微透镜阵列，与形成在衬底表面处的各个光接收结构对准的微透镜和相应的滤色器。 微透镜阵列下面的层间介电材料层的顶表面从密集逻辑布线区域的层间介电材料层的顶表面凹陷。
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