公开(公告)号：US20090158128A1

公开(公告)日：2009-06-18

申请号：US12335834

申请日：2008-12-16

申请人： Takashi Yokokawa ,  Makiko Yamamoto

发明人： Takashi Yokokawa ,  Makiko Yamamoto

IPC分类号： H03M13/05 ,  G06F11/07

CPC分类号： H03M13/45 ,  H03M13/15 ,  H03M13/23 ,  H03M13/2906 ,  H03M13/37

摘要： A decoding device for a linear code on a ring R, the decoding device including: a plurality of storage media; and a processing section; wherein the processing section uses a part of reliability of all symbols at a previous time to update reliability of each symbol in a process of iterative decoding for increasing the reliability of each symbol, and further retains a part used to update retained reliability information and a part unused to update the retained reliability information on two separate storage media.

摘要翻译： 一种用于环R上的线性码的解码装置，所述解码装置包括：多个存储介质; 和处理部; 其中所述处理部分在先前时间使用所有符号的可靠性的一部分来更新迭代解码过程中的每个符号的可靠性，以增加每个符号的可靠性，并且还保留用于更新保留的可靠性信息的部分和部分 未用于在两个单独的存储介质上更新保留的可靠性信息。

公开(公告)号：US07299397B2

公开(公告)日：2007-11-20

申请号：US10521054

申请日：2004-04-19

申请人： Takashi Yokokawa ,  Toshiyuki Miyauchi ,  Yasuhiro Iida

发明人： Takashi Yokokawa ,  Toshiyuki Miyauchi ,  Yasuhiro Iida

IPC分类号： H03M13/00

CPC分类号： H03M13/1168 ,  H03M13/11 ,  H03M13/1114 ,  H03M13/1134 ,  H03M13/1137 ,  H03M13/1145 ,  H03M13/1188 ,  H03M13/6505 ,  H03M13/6566 ,  H03M13/6577

摘要： The present invention relates to a decoding apparatus and a decoding method for realizing the decoding of LDPC codes, in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. A check matrix of LDPC codes is formed by a combination of a (P×P) unit matrix, a matrix in which one to several 1s of the unit matrix are substituted with 0, a matrix in which they are cyclically shifted, a matrix, which is the sum of two or more of them, and a (P×P) 0-matrix. A check node calculator 313 simultaneously performs p check node calculations. A variable node calculator 319 simultaneously performs p variable node calculations.

摘要翻译： 本发明涉及一种用于实现LDPC码的解码的解码装置和解码方法，其中在抑制电路规模的同时，可以在足够可行的范围内抑制工作频率，并且可以执行存储器访问的控制 很容易，也是一个程序。 LDPC码的校验矩阵通过（PxP）单位矩阵，单位矩阵中的一个到数个1被0替换的矩阵，它们被循环移位的矩阵的组合形成矩阵，矩阵是 它们中的两个或更多个的和，以及（PxP）0矩阵。 校验节点计算器313同时执行p校验节点计算。 变量节点计算器319同时执行p变量节点计算。

公开(公告)号：US20070204197A1

公开(公告)日：2007-08-30

申请号：US11640256

申请日：2006-12-18

申请人： Takashi Yokokawa

发明人： Takashi Yokokawa

IPC分类号： H03M13/00

CPC分类号： H03M13/1137 ,  H03M13/1105 ,  H03M13/1111 ,  H03M13/1117 ,  H03M13/1131 ,  H03M13/1134 ,  H03M13/6505 ,  H03M13/6566

摘要： A decoding device for decoding LDPC (Low Density Parity Check) codes includes a message calculation unit for performing a variable node calculation for decoding the LPDC codes using a message to be supplied, or performing a check node calculation, and outputting the message to be obtained as a result of the calculation, a storing unit for storing the message, and a control unit for performing writing control for writing the message that the message calculation unit outputs in the storing unit, and readout control for reading out the same message to be employed for the calculation of the message calculation unit from the storing unit twice, and supplying these to the message calculation unit.

摘要翻译： 用于解码LDPC（低密度奇偶校验）码的解码装置包括消息计算单元，用于使用要提供的消息来执行用于对LPDC码进行解码的可变节点计算，或执行校验节点计算，并输出要获得的消息 作为计算的结果，存储消息的存储单元和用于执行写入控制的控制单元，用于写入消息计算单元在存储单元中输出的消息，以及用于读出要使用的相同消息的读出控制 用于从存储单元计算消息计算单元两次，并将其提供给消息计算单元。

公开(公告)号：US20050240853A1

公开(公告)日：2005-10-27

申请号：US10521054

申请日：2004-04-19

申请人： Takashi Yokokawa ,  Toshiyuki Miyauchi ,  Yasuhiro IIida

发明人： Takashi Yokokawa ,  Toshiyuki Miyauchi ,  Yasuhiro IIida

IPC分类号： G06F11/10 ,  H03M13/11 ,  H03M13/19 ,  H03M13/00

CPC分类号： H03M13/1168 ,  H03M13/11 ,  H03M13/1114 ,  H03M13/1134 ,  H03M13/1137 ,  H03M13/1145 ,  H03M13/1188 ,  H03M13/6505 ,  H03M13/6566 ,  H03M13/6577

摘要： The present invention relates to a decoding apparatus and a decoding method for realizing the decoding of LDPC codes, in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. A check matrix of LDPC codes is formed by a combination of a (P×P) unit matrix, a matrix in which one to several 1s of the unit matrix are substituted with 0, a matrix in which they are cyclically shifted, a matrix, which is the sum of two or more of them, and a (P×P) 0-matrix. A check node calculator 313 simultaneously performs p check node calculations. A variable node calculator 319 simultaneously performs p variable node calculations.

摘要翻译： 本发明涉及一种用于实现LDPC码的解码的解码装置和解码方法，其中在抑制电路规模的同时，可以在足够可行的范围内抑制工作频率，并且可以执行存储器访问的控制 很容易，也是一个程序。 LDPC码的校验矩阵通过（PxP）单位矩阵，单位矩阵中的一个到数个1被0替换的矩阵，它们被循环移位的矩阵的组合形成矩阵，矩阵是 它们中的两个或更多个的和，以及（PxP）0矩阵。 校验节点计算器313同时执行p校验节点计算。 变量节点计算器319同时执行p变量节点计算。

公开(公告)号：US08873679B2

公开(公告)日：2014-10-28

申请号：US12981948

申请日：2010-12-30

申请人： Takashi Yokokawa ,  Satoshi Okada

发明人： Takashi Yokokawa ,  Satoshi Okada

IPC分类号： H04N21/43 ,  H04N21/214 ,  H04W4/00 ,  H04N21/236 ,  H04N21/434 ,  H04H60/40 ,  H04N21/235 ,  H04L27/26 ,  H04N21/2383 ,  H04N21/242 ,  H04N21/438 ,  H04N21/435 ,  H04H40/18

CPC分类号： H04L27/2647 ,  H04H40/18 ,  H04H60/40 ,  H04N21/235 ,  H04N21/23608 ,  H04N21/2383 ,  H04N21/242 ,  H04N21/4302 ,  H04N21/4305 ,  H04N21/434 ,  H04N21/4344 ,  H04N21/4345 ,  H04N21/435 ,  H04N21/4382 ,  H04W56/00 ,  H04W56/001 ,  H04W56/003

摘要： Disclosed herein is a reception apparatus, including: a reception section configured to receive an OFDM (Orthogonal Frequency Division Multiplexed) signal obtained by modulating a common packet sequence configured from a packet common to streams and a data packet sequence configured from packets individually unique to the streams; a time counting section configured to count, using predetermined time indicated by additional information added to particular packets of the common and data packet sequences obtained by demodulating the received OFDM signal as a reference, elapsed time after the predetermined time; a detection section configured to compare the counted time and time indicated by the additional information added to the particular packets of the common and data packet sequences to detect a displacement in the time direction between the packets; and a correction section configured to correct the displacement between the packets of the common and data packet sequences in the time direction.

摘要翻译： 这里公开了一种接收装置，包括：接收部分，被配置为接收通过调制由流公用的分组配置的公共分组序列获得的OFDM（正交频分复用）信号，以及从由 溪流 时间计数部分，被配置为使用通过将通过解调所接收的OFDM信号作为参考获得的公共数据分组序列的特定分组附加的附加信息指定的预定时间进行计数，经过预定时间之后的经过时间; 检测部，被配置为比较由附加到所述公用数据包序列和所述数据包序列的特定分组的附加信息所指示的所计算的时间和时间，以检测所述分组之间的时间方向上的位移; 以及校正部，被配置为在时间方向上校正公用数据包序列和数据包序列的包之间的位移。

公开(公告)号：US08578237B2

公开(公告)日：2013-11-05

申请号：US12744400

申请日：2008-11-26

申请人： Takashi Yokokawa ,  Makiko Yamamoto ,  Satoshi Okada ,  Lui Sakai ,  Ryoji Ikegaya

发明人： Takashi Yokokawa ,  Makiko Yamamoto ,  Satoshi Okada ,  Lui Sakai ,  Ryoji Ikegaya

IPC分类号： H03M13/00

CPC分类号： H03M13/1165 ,  H03M13/036 ,  H03M13/255 ,  H03M13/2703 ,  H03M13/271 ,  H03M13/6552 ,  H04L1/0057 ,  H04L1/0071 ,  H04L27/3416 ,  H04L27/3488

摘要： The present invention relates to a data processing apparatus and a data processing method which can improve the tolerance to errors of data. A demultiplexer replaces, in accordance with an allocation rule for allocating code bits of an LDPC code to symbol bits representative of symbols, mb bits from among the code bits and sets the code bits after the replacement as symbol bits of b symbols. According to the allocation rule, where groups into which the code bits and the symbol bits are to be grouped in response to an error probability thereof are set as code bit groups and symbol bit groups, respectively, a combination of any of the code bit groups and the symbol bit group of the symbol bits to which the code bits of the code bit group are to be allocated and bit numbers of the code bits and the symbols bits are prescribed.

摘要翻译： 数据处理装置和数据处理方法技术领域本发明涉及一种数据处理装置和数据处理方法，其可以提高对数据的误差的容忍度。 解复用器根据用于分配LDPC码的码位的分配规则替换代表码元的符号位，并从代码比特中取代mb比特，并将替换后的码比特设置为b符号的符号比特。 根据分配规则，分别将代码比特和符号比特的组合作为码比特组和符号比特组分别设定为组合的任何编码比特组 以及要分配码位组的码位的符号位的符号位组，以及代码位和符号位的位编号。

公开(公告)号：US08499214B2

公开(公告)日：2013-07-30

申请号：US12743398

申请日：2008-11-26

申请人： Takashi Yokokawa ,  Makiko Yamamoto ,  Satoshi Okada ,  Ryoji Ikegaya

发明人： Takashi Yokokawa ,  Makiko Yamamoto ,  Satoshi Okada ,  Ryoji Ikegaya

IPC分类号： H03M13/00

CPC分类号： H04L27/2647 ,  H03M13/033 ,  H03M13/1165 ,  H03M13/152 ,  H03M13/255 ,  H03M13/2707 ,  H03M13/2906 ,  H03M13/356 ,  H03M13/6552 ,  H03M13/6555

摘要： The present invention relates to a data processing apparatus and a data processing method which can improve the tolerance to errors of data. A demultiplexer 25 replaces, in accordance with an allocation rule for allocating code bits of an LDPC code to symbol bits representative of symbols, mb bits from among the code bits and sets the code bits after the replacement as symbol bits of b symbols. For example, when m is 12 and b is 1, where the i+1th bits from the most significant bit of the 12×1 code bits and the 12×1 symbol bits of one symbol are represented as bits bi and yi, replacement for allocating, for example, b0 to y8, b1 to y0, b2 to y6, b3 to y1, b4 to y4, b5 to y5, b6 to y2, b7 to y3, b8 to y7, b9 to y10, b10 to y11 and b11 to y9 is carried out. The present invention can be applied, for example, to a transmission system for transmitting an LDPC code and so forth.

摘要翻译： 数据处理装置和数据处理方法技术领域本发明涉及一种数据处理装置和数据处理方法，其可以提高对数据的误差的容忍度。 解复用器25根据用于分配LDPC码的码位的分配规则替换代表码元的符号位，并从代码比特中替换mb比特，并将替换后的码比特设置为b符号的符号比特。 例如，当m为12且b为1时，其中来自12×1码位的最高有效位的第i + 1位和一个符号的12×1符号位表示为位bi和yi，替换为 分配例如b0至y8，b1至y0，b2至y6，b3至y1，b4至y4，b5至y5，b6至y2，b7至y3，b8至y7，b9至y10，b10至y11和b11 到y9进行。 本发明可以应用于例如用于发送LDPC码等的传输系统。

公开(公告)号：US08312353B2

公开(公告)日：2012-11-13

申请号：US12335834

申请日：2008-12-16

申请人： Takashi Yokokawa ,  Makiko Yamamoto

发明人： Takashi Yokokawa ,  Makiko Yamamoto

IPC分类号： H03M13/00

CPC分类号： H03M13/45 ,  H03M13/15 ,  H03M13/23 ,  H03M13/2906 ,  H03M13/37

摘要： A decoding device for a linear code on a ring R, the decoding device including: a plurality of storage media; and a processing section; wherein the processing section uses a part of reliability of all symbols at a previous time to update reliability of each symbol in a process of iterative decoding for increasing the reliability of each symbol, and further retains a part used to update retained reliability information and a part unused to update the retained reliability information on two separate storage media.

摘要翻译： 一种用于环R上的线性码的解码装置，所述解码装置包括：多个存储介质; 和处理部; 其中所述处理部分在先前时间使用所有符号的可靠性的一部分来更新迭代解码过程中的每个符号的可靠性，以增加每个符号的可靠性，并且还保留用于更新保留的可靠性信息的部分和部分 未用于在两个单独的存储介质上更新保留的可靠性信息。

公开(公告)号：US20120189079A1

公开(公告)日：2012-07-26

申请号：US13359928

申请日：2012-01-27

申请人： Matthew Paul Athol TAYLOR ,  Samuel Asanbeng Atungsiri ,  Takashi Yokokawa ,  Makiko Yamamoto

发明人： Matthew Paul Athol TAYLOR ,  Samuel Asanbeng Atungsiri ,  Takashi Yokokawa ,  Makiko Yamamoto

IPC分类号： H03M13/05 ,  H04L27/00

CPC分类号： H03M13/1168 ,  H03M13/1137 ,  H03M13/1148 ,  H03M13/116 ,  H03M13/1165 ,  H03M13/1185 ,  H03M13/15 ,  H03M13/152 ,  H03M13/255 ,  H03M13/2707 ,  H03M13/271 ,  H03M13/2906 ,  H04L1/0057 ,  H04L1/0071 ,  H04L5/0007 ,  H04L5/0044 ,  H04L5/0064 ,  H04L27/2626 ,  H04L27/2647 ,  H04L27/34

摘要： A data processing apparatus communicates data bits on a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processing apparatus comprises a parity interleaver operable to perform parity interleaving on Low Density Parity Check (LDPC) encoded data bits obtained by performing LDPC encoding according to a parity check matrix of an LDPC code including a parity matrix corresponding to parity bits of the LDPC code, the parity matrix having a stepwise structure, so that a parity bit of the LDPC encoded data bits is interleaved to a different parity bit position. A mapping unit maps the parity interleaved bits onto data symbols corresponding to modulation symbols of a modulation scheme of the OFDM sub-carrier signals.

摘要翻译： 数据处理装置在正交频分复用（OFDM）符号的预定数量的副载波信号上传送数据位。 数据处理装置包括奇偶校验交织器，其可操作以对通过执行LDPC编码而获得的低密度奇偶校验（LDPC）编码数据比特进行奇偶校验交织，所述LDPC编码数据比特根据LDPC码的奇偶校验矩阵，该LDPC码包括与LDPC码奇偶校验位对应的奇偶校验矩阵 代码，奇偶校验矩阵具有逐步结构，使得LDPC编码数据位的奇偶校验位被交织到不同的奇偶校验位位置。 映射单元将奇偶交织的比特映射到对应于OFDM子载波信号的调制方案的调制符号的数据符号上。

公开(公告)号：US08103945B2

公开(公告)日：2012-01-24

申请号：US11959551

申请日：2007-12-19

申请人： Makiko Yamamoto ,  Satoshi Okada ,  Toshiyuki Miyauchi ,  Takashi Yokokawa

发明人： Makiko Yamamoto ,  Satoshi Okada ,  Toshiyuki Miyauchi ,  Takashi Yokokawa

IPC分类号： G06F11/00

CPC分类号： H03M13/114 ,  H03M13/1111 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/2936 ,  H03M13/2948 ,  H03M13/3905 ,  H03M13/4146

摘要： A decoding method for sorting received words in the order of the magnitude of the reliability of the received words, performing belief propagation using a parity check matrix diagonalized in the order to update the reliabilities, and repetitively performing the sorting and the belief propagation for the updated values, includes an inner repeated decoding process step of performing belief propagation using a parity check matrix diagonalized in an order of columns corresponding to symbols having comparatively low reliability values of the received words to update the reliability and repetitively performing the belief propagation based on the updated reliability; the inner repeated decoding process step in the second or later cycle of repetition thereof including diagonalization of the parity check matrix for restricted ones of the columns of the parity check matrix.

摘要翻译： 一种用于按接收字的可靠性大小的顺序对接收到的字进行分类的解码方法，使用以对等化的奇偶校验矩阵来执行置信传播，以更新可靠性，并且重复地执行用于更新的可更新的排序和置信传播 值包括内部重复解码处理步骤，其使用对应于与所接收到的字的具有相对低的可靠性值的符号相对应的列的顺序对角化的奇偶校验矩阵来执行置信传播，以更新可靠性并基于更新后的重新执行置信传播 可靠性; 内部重复解码处理步骤在其重复的第二或更晚的循环中，包括奇偶校验矩阵的有限列的奇偶校验矩阵的对角化。