公开(公告)号：US07560692B2

公开(公告)日：2009-07-14

申请号：US11617386

申请日：2006-12-28

申请人： Keith E. Barton ,  Steven H. Boettcher ,  John G. Gaudiello ,  Leon J. Kimball ,  Yun-Yu Wang

发明人： Keith E. Barton ,  Steven H. Boettcher ,  John G. Gaudiello ,  Leon J. Kimball ,  Yun-Yu Wang

IPC分类号： G01N1/32 ,  G01N23/04

CPC分类号： G01N1/2806

摘要： A high quality electron microscopy sample suitable for electron holography is prepared by forming markers filled with TEOS oxide and by repeatedly applying multiple coats of an adhesive followed by a relatively low temperature cure after each application. The TEOS oxide marker is readily visible during the polish, has a similar polish rate as a semiconductor material, and reduces contamination during sample preparation. The repeated application of adhesives separated by relatively low temperature cures increases the adhesive strength of the adhesive material to the semiconductor material without making it too brittle. This results in an improved control and yield of the sample preparation process.

摘要翻译： 适用于电子全息术的高品质电子显微镜样品通过形成填充有TEOS氧化物的标记物，并通过反复施加多层粘合剂，然后在每次涂布之后进行相对低温固化来制备。 TEOS氧化物标记在抛光期间容易看到，具有与半导体材料相似的抛光速率，并减少样品制备过程中的污染。 通过相对低温固化分离的粘合剂的重复施加增加了粘合剂材料对半导体材料的粘合强度，而不会使其变得太脆。 这导致样品制备过程的改进的控制和产率。

公开(公告)号：US20090137109A1

公开(公告)日：2009-05-28

申请号：US12364088

申请日：2009-02-02

申请人： Daewon Yang ,  Woo-Hyeong Lee ,  Tai-chi Su ,  Yun-Yu Wang

发明人： Daewon Yang ,  Woo-Hyeong Lee ,  Tai-chi Su ,  Yun-Yu Wang

IPC分类号： H01L21/71

CPC分类号： H01L21/02274 ,  C23C16/345 ,  C23C16/505 ,  H01L21/0217 ,  H01L21/3185 ,  H01L21/76829 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

摘要： Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane, argon and nitrogen; biasing the substrate to a high frequency power of varying density, in a range between 0.8 W/cm2 and 5.0 W/cm2; and depositing the high-density plasma to the plurality of gate structures to form the compressive stress nitride film.

摘要翻译： 本发明的实施例提供一种通过高密度等离子体沉积工艺形成在衬底上产生的多个p型场效应晶体管栅极结构的压应力氮化物膜的形成方法。 实施例包括使用至少硅烷，氩和氮的源气体产生填充有高密度等离子体的环境; 在0.8W / cm 2至5.0W / cm 2之间的范围内将衬底偏置为变化密度的高频功率; 以及将所述高密度等离子体沉积到所述多个栅极结构以形成所述压应力氮化物膜。

公开(公告)号：US20090119357A1

公开(公告)日：2009-05-07

申请号：US11934914

申请日：2007-11-05

申请人： James P. Rice ,  Yunsheng Song ,  Yun-Yu Wang ,  Chienfan Yu

发明人： James P. Rice ,  Yunsheng Song ,  Yun-Yu Wang ,  Chienfan Yu

IPC分类号： G06F17/15

CPC分类号： G06K9/6253

摘要： A method only has the user input (or select) a data type, a report key, a dependent variable table, and/or filtering restrictions. Using this information, the method automatically locates independent variable data based on the data type and the report key. This independent variable data can be in the form of a table and comprises independent variables. The method automatically joins the dependent variable table and the independent variable data to create a joint table. Then, the method can automatically perform a statistical analysis of the joint table to find correlations between the dependent variables and the independent variables and output the correlations, without requiring the user to input or identify the independent variables.

摘要翻译： 方法只有用户输入（或选择）数据类型，报告键，因变量表和/或过滤限制。 使用该信息，该方法根据数据类型和报告密钥自动定位独立的变量数据。 这个独立的变量数据可以是一个表格的形式，并且包括自变量。 该方法自动连接因变量表和独立变量数据以创建联合表。 然后，该方法可以自动执行联合表的统计分析，以找出因变量和独立变量之间的相关性，并输出相关性，而不需要用户输入或识别自变量。

公开(公告)号：US07504337B2

公开(公告)日：2009-03-17

申请号：US11690432

申请日：2007-03-23

申请人： Keith E. Barton ,  Thomas A. Bauer ,  Stanley J. Klepeis ,  John A. Miller ,  Yun-Yu Wang

发明人： Keith E. Barton ,  Thomas A. Bauer ,  Stanley J. Klepeis ,  John A. Miller ,  Yun-Yu Wang

IPC分类号： H01L21/461 ,  H01L21/302

CPC分类号： G01N1/32 ,  H01L22/24

摘要： Methods of uniformly delayering an IC chip are disclosed. One embodiment includes: performing an ash on the wafer including an Al layer thereof and etching the Al layer; polishing an edge of the wafer using a slurry including an approximately 30 μm polishing particles; removing the aluminum layer and at least one metal layer by polishing using a slurry including approximately 9 μm diamond polishing particles and a non-abrasive backside of a polishing sheet; removing any remaining metal layers to a first metal layer by polishing using a slurry including approximately 3 μm diamond polishing particles and the non-abrasive backside of a polishing sheet; removing any scratches by polishing using a slurry including approximately 1 μm diamond polishing particles and the non-abrasive backside of a polishing sheet; and removing the first metal layer to a polyconductor layer by polishing using a colloidal slurry including approximately 0.25 μm diamond polishing particles.

摘要翻译： 公开了均匀地延迟IC芯片的方法。 一个实施例包括：在包括其Al层的晶片上执行灰分并蚀刻Al层; 使用包含约30μm的抛光颗粒的浆料抛光晶片的边缘; 通过使用包含大约9μm的金刚石抛光颗粒和抛光片的非研磨背面的浆料进行抛光来去除铝层和至少一个金属层; 通过使用包含大约3μm的金刚石抛光颗粒和抛光片的非研磨背面的浆料进行抛光，将任何剩余的金属层除去到第一金属层; 通过使用包括大约1毫米金刚石抛光颗粒和抛光片的非研磨背面的浆料进行抛光来除去任何划痕; 并且通过使用包含大约0.25μm金刚石抛光颗粒的胶体浆料进行抛光将第一金属层去除到多导体层。

公开(公告)号：US20090039447A1

公开(公告)日：2009-02-12

申请号：US11834641

申请日：2007-08-06

申请人： Matthew W. Copel ,  Bruce B. Doris ,  Vijay Narayanan ,  Yun-Yu Wang

发明人： Matthew W. Copel ,  Bruce B. Doris ,  Vijay Narayanan ,  Yun-Yu Wang

IPC分类号： H01L29/94 ,  H01L21/336

CPC分类号： H01L29/513 ,  H01L21/28026 ,  H01L21/28229 ,  H01L21/823857 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7833

摘要： A method for fabricating an FET device is disclosed. The FET device has a gate insulator with a high-k dielectric portion, and a threshold modifying material. The method introduces a stabilizing material into the gate insulator in order to hinder one or more metals from the threshold modifying material to penetrate across the high-k portion of the gate insulator. The introduction of the stabilizing material may involve disposing a stabilizing agent over a layer which contains an oxide of the one or more metals. A stabilizing material may also be incorporated into the high-k dielectric. Application of the method may lead to FET devices with unique gate insulator structures.

摘要翻译： 公开了一种用于制造FET器件的方法。 FET器件具有具有高k电介质部分的栅极绝缘体和阈值修饰材料。 该方法将稳定材料引入栅极绝缘体中，以便阻止来自阈值修饰材料的一种或多种金属穿过栅极绝缘体的高k部分。 稳定材料的引入可以包括在包含一种或多种金属的氧化物的层上设置稳定剂。 稳定材料也可以并入高k电介质中。 该方法的应用可能导致具有独特栅极绝缘体结构的FET器件。

公开(公告)号：US20080020535A1

公开(公告)日：2008-01-24

申请号：US11866751

申请日：2007-10-03

申请人： Levent Gulari ,  Kevin Mello ,  Robert Purtell ,  Yun-Yu Wang ,  Keith Wong

发明人： Levent Gulari ,  Kevin Mello ,  Robert Purtell ,  Yun-Yu Wang ,  Keith Wong

IPC分类号： H01L21/336 ,  H01L21/44

CPC分类号： H01L21/28052 ,  H01L21/28114 ,  H01L21/28518 ,  H01L29/665

摘要： A silicide cap structure and method of fabricating a silicide cap having a low sheet resistance. The method provides a semiconductor substrate and a MOSFET structure comprising a gate insulator on the substrate, an Si-containing gate electrode on the gate insulator layer, and source/drain diffusions. Atop the gate electrode and source/drain diffusions is formed a layer of metal used in forming a silicide region atop the transistor gate electrode and diffusions; an intermediate metal barrier layer formed atop the silicide forming metal layer; and, an oxygen barrier layer formed atop the intermediate metal barrier layer. As a result of annealing the MOSFET structure, resulting formed silicide regions exhibit a lower sheet resistance. As the intermediate metal barrier layer comprises a material exhibiting tensile stress, the oxygen barrier layer may comprise a compressive material for minimizing a total mechanical stress of the cap structure and underlying layers during the applied anneal.

摘要翻译： 一种硅化物盖结构和制造具有低薄层电阻的硅化物盖的方法。 该方法提供半导体衬底和MOSFET结构，其包括在衬底上的栅极绝缘体，栅极绝缘体层上的含Si栅极电极和源极/漏极扩散。 在栅电极和源极/漏极扩散之上形成用于在晶体管栅极顶部形成硅化物区域和扩散的金属层; 形成在所述硅化物形成金属层顶上的中间金属阻挡层; 以及形成在中间金属阻挡层顶上的氧阻隔层。 作为对MOSFET结构进行退火的结果，所形成的形成的硅化物区域具有较低的薄层电阻。 当中间金属阻挡层包括显示拉伸应力的材料时，氧阻挡层可以包括用于在施加的退火期间最小化盖结构和下层的总机械应力的压缩材料。

公开(公告)号：US20070269992A1

公开(公告)日：2007-11-22

申请号：US11419217

申请日：2006-05-19

申请人： Daewon Yang ,  Woo-Hyeong Lee ,  Tai-chi Su ,  Yun-Yu Wang

发明人： Daewon Yang ,  Woo-Hyeong Lee ,  Tai-chi Su ,  Yun-Yu Wang

IPC分类号： H01L21/31 ,  H01L21/4763 ,  H01L21/3205

CPC分类号： H01L21/02274 ,  C23C16/345 ,  C23C16/505 ,  H01L21/0217 ,  H01L21/3185 ,  H01L21/76829 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

摘要： Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane, argon and nitrogen; biasing the substrate to a high frequency power of varying density, in a range between 0.8 W/cm2 and 5.0 W/cm2; and depositing the high-density plasma to the plurality of gate structures to form the compressive stress nitride film.

摘要翻译： 本发明的实施例提供一种通过高密度等离子体沉积工艺形成在衬底上产生的多个p型场效应晶体管栅极结构的压应力氮化物膜的形成方法。 实施例包括使用至少硅烷，氩和氮的源气体产生填充有高密度等离子体的环境; 在0.8W / cm 2和5.0W / cm 2之间的范围内将衬底偏置为变化密度的高频功率; 以及将所述高密度等离子体沉积到所述多个栅极结构以形成所述压应力氮化物膜。

公开(公告)号：US20070269970A1

公开(公告)日：2007-11-22

申请号：US11419300

申请日：2006-05-19

申请人： Robert J. Purtell ,  Henry K. Utomo ,  Yun-Yu Wang ,  Haining S. Yang

发明人： Robert J. Purtell ,  Henry K. Utomo ,  Yun-Yu Wang ,  Haining S. Yang

IPC分类号： H01L21/28

CPC分类号： H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/517 ,  H01L29/665 ,  H01L29/7845

摘要： The present invention provides a semiconductor device comprising at least one field effect transistor (FET) having source and drain (S/D) metal silicide layers with intrinsic tensile or compressive stress. First, a metal layer containing a silicide metal M is formed over S/D regions of a FET, followed by a first annealing step to form S/D metal silicide layers that comprise a metal silicide of a first phase (MSix). A silicon nitride layer is then formed over the FET, followed by a second annealing step. During the second annealing step, the metal silicide is converted from the first phase (MSix) into a second phase (MSiy) with x

摘要翻译： 本发明提供一种半导体器件，其包括至少一个场效应晶体管（FET），该场效应晶体管具有固有的拉伸或压缩应力的源极和漏极（S / D）金属硅化物层。 首先，在FET的S / D区域上形成含有硅化物金属M的金属层，接着进行第一退火工序，形成包含第一相的金属硅化物的S / D金属硅化物层（MSi× ）。 然后在FET上形成氮化硅层，接着进行第二退火步骤。 在第二退火步骤期间，将金属硅化物从第一相（MSi x S x）转换成具有x

公开(公告)号：US20070267386A1

公开(公告)日：2007-11-22

申请号：US11833283

申请日：2007-08-03

申请人： Kaushik Chanda ,  James Demarest ,  Ronald Filippi ,  Roy Iggulden ,  Edward Kiewra ,  Ping-Chuan Wang ,  Yun-Yu Wang

发明人： Kaushik Chanda ,  James Demarest ,  Ronald Filippi ,  Roy Iggulden ,  Edward Kiewra ,  Ping-Chuan Wang ,  Yun-Yu Wang

IPC分类号： H01B13/00 ,  B44C1/22

CPC分类号： B24B37/042 ,  H01L21/31144 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76885 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49204

摘要： Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.

摘要翻译： 公开了一种镶嵌和双镶嵌工艺，其中两者都结合使用剥离层以在金属互连线之间移除痕量的残余材料。 释放层沉积在电介质层上。 释放层包括有机材料，电介质材料，金属或金属氮化物。 沟槽蚀刻到电介质层中。 沟槽内衬衬里，填充导体。 导体和衬里材料从剥离层抛光。 然而，痕量的剩余材料可能会残留。 去除脱模层（例如，通过适当的溶剂或湿蚀刻工艺）以除去残留的材料。 如果沟槽形成为使得剥离层与沟槽的壁重叠，则当除去剥离层时，可以沉积另外的介电层，加强围绕金属互连线的顶部的拐角。

公开(公告)号：US07287325B2

公开(公告)日：2007-10-30

申请号：US10908392

申请日：2005-05-10

申请人： Kaushik Chanda ,  James J. Demarest ,  Ronald G. Filippi ,  Roy C. Iggulden ,  Edward W. Kiewra ,  Ping-Chuan Wang ,  Yun-Yu Wang

发明人： Kaushik Chanda ,  James J. Demarest ,  Ronald G. Filippi ,  Roy C. Iggulden ,  Edward W. Kiewra ,  Ping-Chuan Wang ,  Yun-Yu Wang

IPC分类号： H01K3/10

CPC分类号： B24B37/042 ,  H01L21/31144 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76885 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49204

摘要： Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.

摘要翻译： 公开了一种镶嵌和双镶嵌工艺，其中两者都结合使用剥离层以在金属互连线之间移除痕量的残余材料。 释放层沉积在电介质层上。 释放层包括有机材料，电介质材料，金属或金属氮化物。 沟槽蚀刻到电介质层中。 沟槽内衬衬里，填充导体。 导体和衬里材料从剥离层抛光。 然而，痕量的剩余材料可能会残留。 去除脱模层（例如，通过适当的溶剂或湿蚀刻工艺）以除去残留的材料。 如果沟槽形成为使得剥离层与沟槽的壁重叠，则当除去剥离层时，可以沉积另外的介电层，加强围绕金属互连线的顶部的拐角。