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    Memory device and method of fabricating a memory device
    62.
    发明申请
    Memory device and method of fabricating a memory device 审中-公开
    存储器件和制造存储器件的方法

    公开(公告)号：US20080149978A1

    公开(公告)日：2008-06-26

    申请号：US11645124

    申请日：2006-12-21

    申请人： Till Schloesser

    发明人： Till Schloesser

    IPC分类号： H01L27/108 ,  H01L21/768

    CPC分类号： H01L21/76885 ,  H01L21/76877 ,  H01L27/0207 ,  H01L27/10855

    摘要： A memory device, comprising a semiconductor substrate with at least one storage cell, the storage cell comprising a storage element and a selection transistor, wherein the memory device further comprises a storage element contact assigned to the storage cell, the storage element contact extending from the selection transistor to the storage element along an axis that at least partially runs obliquely with respect to a direction perpendicular to the substrate surface.

    摘要翻译： 一种存储器件，包括具有至少一个存储单元的半导体衬底，所述存储单元包括存储元件和选择晶体管，其中所述存储器件还包括分配给所述存储单元的存储元件触点，所述存储元件触点从 选择晶体管沿着至少部分地相对于垂直于衬底表面的方向倾斜地运行的轴线移动到存储元件。

    Transistor and memory cell array
    63.
    发明申请
    Transistor and memory cell array 有权
    晶体管和存储单元阵列

    公开(公告)号：US20080121961A1

    公开(公告)日：2008-05-29

    申请号：US11517558

    申请日：2006-09-08

    申请人： Till Schloesser

    发明人： Till Schloesser

    IPC分类号： H01L27/088 ,  H01L29/78 ,  G11C11/34 ,  H01L21/77

    CPC分类号： H01L27/10891 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/11507

    摘要： A transistor, which is formed in a semiconductor substrate having a top surface, includes first and second source/drain regions, a channel connecting the first and second source/drain regions, and a gate electrode for controlling an electrical current flowing in the channel. The gate electrode is disposed in a lower portion of a gate groove defined in the top surface of the semiconductor substrate. The upper portion of the groove is filled with an insulating material. The channel includes a fin-like portion in the shape of a ridge having a top side and two lateral sides in a cross-section perpendicular to a direction defined by a line connecting the first and second source/drain regions. The gate electrode encloses the channel at the top side and the two lateral sides thereof.

    摘要翻译： 形成在具有顶表面的半导体衬底中的晶体管包括第一和第二源极/漏极区域，连接第一和第二源极/漏极区域的沟道以及用于控制在沟道中流动的电流的栅电极。 栅电极设置在限定在半导体衬底的顶表面中的栅极沟槽的下部。 槽的上部填充有绝缘材料。 通道包括脊形状的翅片状部分，其具有垂直于由连接第一和第二源极/漏极区域的线限定的方向的横截面中的顶侧和两个侧面。 栅电极在其顶侧和其两个侧面包围通道。

    Memory Cell Array
    64.
    发明申请
    Memory Cell Array 有权
    存储单元阵列

    公开(公告)号：US20080089114A1

    公开(公告)日：2008-04-17

    申请号：US11945437

    申请日：2007-11-27

    申请人： Till Schloesser

    发明人： Till Schloesser

    IPC分类号： G11C11/00

    CPC分类号： H01L27/10814 ,  G11C5/063 ,  G11C7/18 ,  G11C11/403 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/0214 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891 ,  H01L27/11507

    摘要： A memory cell array includes memory cells, bit lines running along a first direction, word lines running along a second direction perpendicular to the first direction, and continuous active area lines, wherein transistors are at least partially formed in the active area lines. The transistors electrically couple corresponding memory cells to corresponding bit lines via bit line contacts, and the transistors are addressed by the word lines. The bit line contacts are formed in a region generally defined by an intersection of a bit line and a corresponding active area line. Neighboring bit line contacts which are connected with one active area line are connected with neighboring bit lines. Consequently, one active area line is crossed by a plurality of bit lines.

    摘要翻译： 存储单元阵列包括存储单元，沿着第一方向延伸的位线，沿垂直于第一方向的第二方向延伸的字线，以及连续有源区线，其中晶体管至少部分地形成在有源区域线中。 晶体管通过位线触点将对应的存储器单元电耦合到对应的位线，并且晶体管由字线寻址。 位线触点形成在通常由位线和相应的有源区域线的交点限定的区域中。 与一个有源区域线连接的相邻位线触点与相邻位线连接。 因此，一个有效面积线被多个位线交叉。

    6F2 access transistor arrangement and semiconductor memory device
    66.
    发明申请
    6F2 access transistor arrangement and semiconductor memory device 有权
    6F2存取晶体管布置和半导体存储器件

    公开(公告)号：US20060281250A1

    公开(公告)日：2006-12-14

    申请号：US11011040

    申请日：2004-12-15

    申请人： Till Schloesser

    发明人： Till Schloesser

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/0207 ,  H01L21/76232 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10897

    摘要： An access transistor arrangement is provided for a 6F2 stacked capacitor DRAM memory cell layout with shared bit line contacts. The access transistors are arranged in pairs along semiconductor lines. The two transistors of each pair of transistors are arranged laterally reversed opposing the respective common bit line section. Each pair of access transistors is separated from the adjacent pair of access transistors by an isolation transistor which is permanently turned off. The access transistors and the isolation transistors are formed as identical recessed channel transistors with elongated channel and enhanced isolation properties. The same dopant concentration may be provided for both junctions of the access transistors. As identical devices are provided both as access transistor and as isolation transistors, the complexity of lithographic patterning processes is reduced.

    摘要翻译： 为具有共享位线触点的6F 2堆叠电容器DRAM存储单元布局提供存取晶体管布置。 存取晶体管沿着半导体线成对配置。 每对晶体管的两个晶体管被布置成相对于相应的公共位线部分横向反转。 每对存取晶体管通过永久关闭的隔离晶体管与相邻的一对存取晶体管分离。 存取晶体管和隔离晶体管形成为具有细长沟道和增强隔离性能的相同的凹槽通道晶体管。 可以为存取晶体管的两个结提供相同的掺杂剂浓度。 由于作为存取晶体管和隔离晶体管都提供相同的器件，因此降低了光刻图案化工艺的复杂性。

    Memory cell array
    67.
    发明授权
    Memory cell array 有权
    存储单元阵列

    公开(公告)号：US07139184B2

    公开(公告)日：2006-11-21

    申请号：US11004881

    申请日：2004-12-07

    申请人： Till Schloesser

    发明人： Till Schloesser

    IPC分类号： G11C7/02

    CPC分类号： H01L27/10814 ,  G11C5/063 ,  G11C7/18 ,  G11C11/403 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/0214 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891 ,  H01L27/11507

    摘要： A memory cell array includes memory cells, bit lines running along a first direction, word lines running along a second direction perpendicular to the first direction, and continuous active area lines, wherein transistors are at least partially formed in the active area lines. The transistors electrically couple corresponding memory cells to corresponding bit lines via bit line contacts, and the transistors are addressed by the word lines. The bit line contacts are formed in a region generally defined by an intersection of a bit line and a corresponding active area line. Neighboring bit line contacts which are connected with one active area line are connected with neighboring bit lines. Consequently, one active area line is crossed by a plurality of bit lines.

    摘要翻译： 存储单元阵列包括存储单元，沿着第一方向延伸的位线，沿垂直于第一方向的第二方向延伸的字线，以及连续有源区线，其中晶体管至少部分地形成在有源区域线中。 晶体管通过位线触点将对应的存储器单元电耦合到对应的位线，并且晶体管由字线寻址。 位线触点形成在通常由位线和相应的有源区域线的交点限定的区域中。 与一个有源区域线连接的相邻位线触点与相邻位线连接。 因此，一个有效面积线被多个位线交叉。