公开(公告)号：US07221584B2

公开(公告)日：2007-05-22

申请号：US11053379

申请日：2005-02-08

申请人： Chi-Wen Liu ,  Kuo-Ching Chiang ,  Horng-Huei Tseng ,  Denny D. Tang

发明人： Chi-Wen Liu ,  Kuo-Ching Chiang ,  Horng-Huei Tseng ,  Denny D. Tang

IPC分类号： G11C11/00 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/228

摘要： A magnetic memory includes two first magnetic layers each oriented over a substrate, a second magnetic layer interposing the two first magnetic layers, and two dielectric layers each contacting the second magnetic layer and interposing the second magnetic layer and one of the two first magnetic layers. Each of the first and second magnetic layers and the dielectric layers may be oriented substantially perpendicular to the substrate or at an acute angle relative to the substrate.

摘要翻译： 磁存储器包括两个分别定向在衬底上的第一磁性层，插入两个第一磁性层的第二磁性层和与第二磁性层接触并插入第二磁性层和两个第一磁性层之一的两个电介质层。 第一和第二磁性层和电介质层中的每一个可以基本上垂直于衬底取向或相对于衬底成锐角。

公开(公告)号：US20060163735A1

公开(公告)日：2006-07-27

申请号：US11357697

申请日：2006-02-17

申请人： Horng-Huei Tseng

发明人： Horng-Huei Tseng

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L21/76846 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76864 ,  H01L21/76877 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A damascene structure and process at semiconductor substrate level. A pre-metal dielectric layer is provided on a semiconductor substrate with an opening exposing a contact region on the substrate. A buffer metal layer is provided on the exposed contact region, and a barrier layer is provided on the interior of the opening. A conductor is provided on the buffer metal layer, substantially filling the opening to electrically connect to the contact region.

摘要翻译： 半导体衬底级别的镶嵌结构和工艺。 在半导体衬底上设置预金属电介质层，该开口露出衬底上的接触区域。 在暴露的接触区域上设置有缓冲金属层，在开口的内部设有阻挡层。 导体设置在缓冲金属层上，基本上填充开口以电连接到接触区域。

公开(公告)号：US20060043463A1

公开(公告)日：2006-03-02

申请号：US10932198

申请日：2004-09-01

申请人： Chi-Wen Liu ,  Kuo-Ching Chiang ,  Horng-Huei Tseng ,  Wen-Tin Chu

发明人： Chi-Wen Liu ,  Kuo-Ching Chiang ,  Horng-Huei Tseng ,  Wen-Tin Chu

IPC分类号： H01L29/788

CPC分类号： H01L21/28194 ,  H01L21/28202 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/517 ,  H01L29/518

摘要： A semiconductor device includes a source and a drain formed in a substrate, a tunneling dielectric formed on the substrate between the source and the drain, and a floating gate disposed over the tunneling dielectric having a band-gap energy less than the energy band-gap of silicon.

摘要翻译： 半导体器件包括形成在衬底中的源极和漏极，形成在源极和漏极之间的衬底上的隧道电介质，以及设置在隧道电介质上的浮置栅极，其带隙能量小于能带隙能量 的硅。

公开(公告)号：US20060033133A1

公开(公告)日：2006-02-16

申请号：US11053379

申请日：2005-02-08

申请人： Chi-Wen Liu ,  Kuo-Ching Chiang ,  Horng-Huei Tseng ,  Denny Tang

发明人： Chi-Wen Liu ,  Kuo-Ching Chiang ,  Horng-Huei Tseng ,  Denny Tang

IPC分类号： H01L29/94

CPC分类号： H01L27/228

摘要： A magnetic memory includes two first magnetic layers each oriented over a substrate, a second magnetic layer interposing the two first magnetic layers, and two dielectric layers each contacting the second magnetic layer and interposing the second magnetic layer and one of the two first magnetic layers. Each of the first and second magnetic layers and the dielectric layers may be oriented substantially perpendicular to the substrate or at an acute angle relative to the substrate.

摘要翻译： 磁存储器包括两个分别定向在衬底上的第一磁性层，插入两个第一磁性层的第二磁性层和与第二磁性层接触并插入第二磁性层和两个第一磁性层之一的两个电介质层。 第一和第二磁性层和电介质层中的每一个可以基本上垂直于衬底取向或相对于衬底成锐角。

公开(公告)号：US20060028626A1

公开(公告)日：2006-02-09

申请号：US10910480

申请日：2004-08-03

申请人： Ching-Yu Chang ,  Chien-Hung Lin ,  Chin-Hsiang Lin ,  David Lu ,  Horng-Huei Tseng ,  Burn-Jeng Lin

发明人： Ching-Yu Chang ,  Chien-Hung Lin ,  Chin-Hsiang Lin ,  David Lu ,  Horng-Huei Tseng ,  Burn-Jeng Lin

IPC分类号： G03B27/52

CPC分类号： G03F7/70341

摘要： A megasonic immersion lithography exposure apparatus and method for substantially eliminating microbubbles from an exposure liquid in immersion lithography is disclosed. The apparatus includes an optical system for projecting light through a mask and onto a wafer. An optical transfer chamber is provided adjacent to the optical system for containing an exposure liquid. At least one megasonic plate operably engages the optical transfer chamber for inducing sonic waves in and eliminating microbubbles from the exposure liquid.

摘要翻译： 公开了一种用于在浸没式光刻中基本上消除曝光液体中的微泡的兆声浸没式光刻曝光装置和方法。 该装置包括用于通过掩模将光投射到晶片上的光学系统。 光学传递室邻近光学系统设置，用于容纳曝光液体。 至少一个兆欧表板可操作地接合光学传递室，用于在曝光液体中引入声波并消除微泡。

公开(公告)号：US20050286030A1

公开(公告)日：2005-12-29

申请号：US11009505

申请日：2004-12-10

申请人： Jen-Chieh Shih ,  Burn-Jeng Lin ,  Tsai-Sheng Gau ,  Ru-Gun Liu ,  Chun-Kuang Chen ,  Chin-Hsiang Lin ,  Horng-Huei Tseng

发明人： Jen-Chieh Shih ,  Burn-Jeng Lin ,  Tsai-Sheng Gau ,  Ru-Gun Liu ,  Chun-Kuang Chen ,  Chin-Hsiang Lin ,  Horng-Huei Tseng

IPC分类号： G03B27/52 ,  G03F7/20

CPC分类号： G03F7/70341

摘要： An immersion optical projection system for photolithography is provided. A transparent plate is located between a last lens element and the wafer during a usage of the system. The transparent plate has a lens-side surface and a wafer-side surface. The system is adapted to have a layer of lens-side fluid located between the last lens element and the lens-side surface of the transparent plate, e.g., when the last lens element is operably located over the wafer during a photolithography process. The system is also adapted to have a layer of wafer-side fluid located between the wafer-side surface of the transparent plate and the wafer, during a usage of the system. The wafer-side fluid may or may not be fluidly connected to the lens-side fluid. The wafer-side fluid may or may not differ from the lens-side fluid.

摘要翻译： 提供了一种用于光刻的浸没式光学投影系统。 在使用系统期间，透明板位于最后一个透镜元件和晶片之间。 透明板具有透镜侧表面和晶片侧表面。 该系统适于具有位于最后透镜元件和透明板的透镜侧表面之间的透镜侧流体层，例如当光刻工艺期间最后一个透镜元件可操作地位于晶片上方时。 该系统还适于在系统的使用期间具有位于透明板的晶片侧表面和晶片之间的晶片侧流体层。 晶片侧流体可以或可以不流体地连接到透镜侧流体。 晶片侧流体可以或可以不与透镜侧流体不同。

公开(公告)号：US06958291B2

公开(公告)日：2005-10-25

申请号：US10654757

申请日：2003-09-04

申请人： Chen-Hua Yu ,  Horng-Huei Tseng ,  Syun-Ming Jang ,  Chenming Hu

发明人： Chen-Hua Yu ,  Horng-Huei Tseng ,  Syun-Ming Jang ,  Chenming Hu

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76846

摘要： Composite ALD-formed diffusion barrier layers. In a preferred embodiment, a composite conductive layer is composed of a diffusion barrier layer and/or a low-resistivity metal layer formed by atomic layer deposition (ALD) lining a damascene opening in dielectrics, serving as diffusion blocking and/or adhesion improvement. The preferred composite diffusion barrier layers are dual titanium nitride layers or dual tantalum nitride layers, triply laminar of tantalum, tantalum nitride and tantalum-rich nitride, or tantalum, tantalum nitride and tantalum, formed sequentially on the opening by way of ALD.

摘要翻译： 复合ALD形成的扩散阻挡层。 在优选实施例中，复合导电层由扩散阻挡层和/或由电介质中的镶嵌开口衬底的原子层沉积（ALD）形成的低电阻金属层组成，用作扩散阻挡和/或粘附改善。 优选的复合扩散阻挡层是通过ALD在开口上依次形成的双氮化钛层或双氮化钽层，三层层状的钽，氮化钽和富钽的氮化物，或钽，氮化钽和钽。

公开(公告)号：US20050156156A1

公开(公告)日：2005-07-21

申请号：US11032403

申请日：2005-01-10

申请人： Horng-Huei Tseng ,  Jyh-Chyurn Guo ,  Chenming Hu ,  Da-Chi Lin

发明人： Horng-Huei Tseng ,  Jyh-Chyurn Guo ,  Chenming Hu ,  Da-Chi Lin

IPC分类号： H01L21/762 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L29/7842 ,  H01L21/76232 ,  H01L21/76264 ,  H01L21/76283 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a semiconductor transistor device including a substrate having at least two regions, a semiconductive region extending to a first surface of the substrate and an insulative region extending to a second surface of the substrate. The semiconductor transistor device also includes a patterned semiconductor structure overlying both surfaces of the substrate. The patterned semiconductor structure includes a source or drain region overlying the second surface of the substrate. The semiconductor transistor device further includes a patterned gate structure overlying the patterned semiconductor structure.

摘要翻译： 提供了一种半导体晶体管器件，其包括具有至少两个区域的衬底，延伸到衬底的第一表面的半导体区域和延伸到衬底的第二表面的绝缘区域。 半导体晶体管器件还包括覆盖在衬底的两个表面上的图案化半导体结构。 图案化的半导体结构包括覆盖在衬底的第二表面上的源极或漏极区域。 半导体晶体管器件还包括覆盖图案化半导体结构的图案化栅极结构。

公开(公告)号：US06677224B2

公开(公告)日：2004-01-13

申请号：US09976823

申请日：2001-10-12

申请人： Horng-Huei Tseng

发明人： Horng-Huei Tseng

IPC分类号： H01L213205

CPC分类号： H01L27/11521 ,  H01L21/76224 ,  H01L27/115

摘要： The method of the present invention includes the steps of forming doped regions in the semiconductor substrate. A pad oxide layer is formed on the semiconductor substrate. A masking layer is formed on the pad oxide layer. A masking layer, the pad oxide layer and the semiconductor substrate are patterned to form a trench therein. A gap-filling material is refilled into the trench and over the semiconductor substrate. A portion of the gap-filling material is removed to an upper surface of the masking layer. Next step is to remove the masking layer. A first conductive layer is formed along the surface of the substrate, then removing a portion of the first conductive layer to expose an upper surface of the gap-filling material. An inter polysilicon dielectric layer is formed on the first conductive layer and a second conductive layer is formed on the inter polysilicon dielectric layer.

摘要翻译： 本发明的方法包括在半导体衬底中形成掺杂区的步骤。 在半导体衬底上形成衬垫氧化物层。 在衬垫氧化物层上形成掩模层。 掩模层，衬垫氧化物层和半导体衬底被图案化以在其中形成沟槽。 间隙填充材料被再填充到沟槽中并在半导体衬底上。 间隙填充材料的一部分被去除到掩模层的上表面。 下一步是去除掩模层。 沿着衬底的表面形成第一导电层，然后去除第一导电层的一部分以暴露间隙填充材料的上表面。 在第一导电层上形成多晶硅间介质层，在多晶硅间介质层上形成第二导电层。

公开(公告)号：US06589840B2

公开(公告)日：2003-07-08

申请号：US09891408

申请日：2001-06-27

申请人： Horng-Huei Tseng

发明人： Horng-Huei Tseng

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  Y10S257/90

摘要： A nonvolatile memory device with a reduced size floating gate and an increased coupling ratio is disclosed. The nonvolatile memory device includes two isolation structures protruding above a semiconductor substrate. Two dielectric spacers are disposed on a pair of opposing sidewalls of the two isolation structures. The two dielectric spacers are spaced from one another at a distance that defines a gate width which is beyond lithography limit. A tunnel dielectric and a floating gate are provided on substrate and confined between the two dielectric spacers. The floating gate has a smaller bottom surface area relative to its top surface area and has a surface substantially coplanar with a surface of the isolation structures. On the coplanar surface, an inter-gate dielectric and a control gate are provided. Optionally, a lightly doped region is provided beside the floating gate 118 and within the substrate. A manufacturing method for forming such memory device is also disclosed.

摘要翻译： 公开了一种具有减小尺寸的浮动栅极和增加的耦合比的非易失性存储器件。 非易失性存储器件包括在半导体衬底上突出的两个隔离结构。 两个电介质间隔物设置在两个隔离结构的一对相对的侧壁上。 两个电介质间隔物以限定超出光刻极限的栅极宽度的距离彼此间隔开。 隧道电介质和浮栅设置在衬底上并被限制在两个电介质间隔物之间​​。 浮动栅极相对于其顶表面区域具有较小的底表面积，并且具有与隔离结构的表面基本上共面的表面。 在共面上设置栅极间电介质和控制栅极。 可选地，在浮置栅极118旁边和衬底内设置轻掺杂区域。 还公开了一种用于形成这种存储器件的制造方法。