公开(公告)号：US20200250090A1

公开(公告)日：2020-08-06

申请号：US16652234

申请日：2018-10-03

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Christopher Haywood

IPC: G06F12/0804 ,  G06F12/12

Abstract: A hybrid volatile/non-volatile memory module employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM). A module controller prioritizes accesses to the DRAM cache for improved speed performance and to minimize programming cycles to the NVM. Data is first written to the DRAM cache where it can be accessed (written to and read from) without the aid of the NVM. Data is only written to the NVM when that data is evicted from the DRAM cache to make room for additional data. Mapping tables relating NVM addresses to physical addresses are distributed throughout the DRAM cache using cache line bits that are not used for data.

公开(公告)号：US10649930B2

公开(公告)日：2020-05-12

申请号：US16243055

申请日：2019-01-08

Applicant: Rambus Inc.

Inventor： John Eric Linstadt

IPC: G06F13/16 ,  G06F12/02 ,  G11C7/10 ,  G06F12/06 ,  G11C7/20 ,  G11C7/22

Abstract: A memory controller interfaces with one or more memory devices having configurable width data buses and configurable connectivity between data pins of the memory devices and data pins of the memory controller. Upon initialization of the memory devices, the memory controller automatically discovers the connectivity configuration of the one or more memory devices, including both individually selected and jointly selected devices. After discovering connectivity of the connected devices, the memory controller configures the memory devices according to the discovered connectivity and assigns unique addresses to jointly selected devices.

公开(公告)号：US10509448B2

公开(公告)日：2019-12-17

申请号：US15243596

申请日：2016-08-22

Applicant: RAMBUS INC.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Patrick R. Gill

IPC: G06F1/20 ,  F25B49/00 ,  G06F1/26 ,  H05K7/20 ,  H01B12/02 ,  H01R4/68 ,  H01L39/02 ,  H02G15/34

Abstract: The embodiments herein describe technologies of cryogenic digital systems with a power supply located in an ambient temperature domain and logic located in a cryogenic temperature domain. A pair of conductors is operable to carry current with a voltage difference between the power supply and the logic. The pair of conductors includes a first portion thermally coupled to a temperature-regulated or temperature-controlled intermediate temperature domain. The intermediate temperature domain is less than the ambient temperature domain and greater than the cryogenic temperature domain.

公开(公告)号：US10481973B2

公开(公告)日：2019-11-19

申请号：US15907210

申请日：2018-02-27

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent S. Haukness ,  John Eric Linstadt ,  Scott C. Best

IPC: G06F11/00 ,  G06F11/10 ,  G11C29/42 ,  G11C29/44 ,  G11C5/04 ,  G11C29/04

Abstract: A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.

公开(公告)号：US10388396B2

公开(公告)日：2019-08-20

申请号：US15506621

申请日：2015-08-17

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  John Eric Linstadt ,  Paul William Roukema

IPC: G11C29/00 ,  G11C29/44 ,  G11C5/04 ,  G11C11/401 ,  G11C29/02 ,  G11C29/52

Abstract: A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.

公开(公告)号：US20190237130A1

公开(公告)日：2019-08-01

申请号：US16261937

申请日：2019-01-30

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Thomas Vogelsang

IPC: G11C11/4093 ,  G11C11/4097 ,  G11C11/4076 ,  G11C11/4094

CPC classification number: G11C11/4093 ,  G11C11/4076 ,  G11C11/4094 ,  G11C11/4097

Abstract: A memory stack comprises at least two memory components. The memory components have a first data link interface and are to transmit signals on a data link coupled to the first data link interface at a first voltage level. A buffer component has a second data link interface coupled to the data link. The buffer component is to receive signals on the second data link interface at the first voltage level. A level shifting latch produces a second voltage level in response to receiving the signals at the second data link interface, where the second voltage level is higher than the first voltage level.

公开(公告)号：US20190220222A1

公开(公告)日：2019-07-18

申请号：US16329051

申请日：2017-07-07

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Torsten Partsch

IPC: G06F3/06 ,  G11C7/10 ,  G11C7/06 ,  G11C7/22 ,  H01L25/065 ,  G06F13/16

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06F13/1668 ,  G06F2213/16 ,  G11C7/06 ,  G11C7/1015 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/107 ,  G11C2207/2272 ,  G11C2207/2281 ,  G11C2207/229 ,  H01L25/0657 ,  H01L2225/06541

Abstract: First data is read out of a core storage array of a memory component over a first time interval constrained by data output bandwidth of the core storage array. After read out from the core storage array, the first data is output from the memory component over a second time interval that is shorter than the first time interval and that corresponds to a data transfer bandwidth greater than the data output bandwidth of the core storage array.

公开(公告)号：US10204063B2

公开(公告)日：2019-02-12

申请号：US15867646

申请日：2018-01-10

Applicant: Rambus Inc.

Inventor： John Eric Linstadt

IPC: G06F12/00 ,  G06F13/16 ,  G06F12/06 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G06F12/02

Abstract: A memory controller interfaces with one or more memory devices having configurable width data buses and configurable connectivity between data pins of the memory devices and data pins of the memory controller. Upon initialization of the memory devices, the memory controller automatically discovers the connectivity configuration of the one or more memory devices, including both individually selected and jointly selected devices. After discovering connectivity of the connected devices, the memory controller configures the memory devices according to the discovered connectivity and assigns unique addresses to jointly selected devices.

公开(公告)号：US10177749B2

公开(公告)日：2019-01-08

申请号：US15478757

申请日：2017-04-04

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Carl W. Werner

IPC: H03K5/22 ,  H04L25/02 ,  H03K3/38 ,  H03K19/0175 ,  H03K19/195

Abstract: In an integrated-circuit component having a signal transmitter receives a transmitter power supply that cycles periodically between power-off and power-on voltage levels to define a sequence of enable intervals during which the signal transmitter is to output voltage levels corresponding to respective transmit data bits onto an external signaling link. The signal transmitter generates, at the start of each output-enable interval, an initial nonzero voltage having a first polarity across conductors of the external signaling link, and then conditionally transitions the initial nonzero voltage to a second nonzero voltage according to whether the transmit data bit corresponding to the output-enable interval has a predetermined one of two binary states, the second nonzero voltage having a polarity opposite the first polarity.

公开(公告)号：US20180350411A1

公开(公告)日：2018-12-06

申请号：US15779977

申请日：2016-12-01

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Carl W. Werner

IPC: G11C7/04 ,  G11C7/22 ,  G11C29/02 ,  G11C29/50 ,  H01L39/22 ,  G06F1/12 ,  H03K5/15

CPC classification number: G06F1/12 ,  G11C7/04 ,  G11C7/222 ,  G11C29/022 ,  G11C29/023 ,  G11C29/50012 ,  G11C2207/2254 ,  H03K5/15

Abstract: In a chip-to-chip signaling system includes at least one signaling link coupled between first and second ICs, the first IC has an interface coupled to the signaling link and timed by a first interface timing signal. The second IC has an interface coupled to the signaling link and timed by a second interface timing signal that is mesochronous with respect to the first interface timing signal. The second IC further has phase adjustment circuitry that adjusts a phase of the second interface timing signal using a digital counter implemented with Josephson-junction circuit elements.