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107 条记录 (耗时 0.032 秒)

    Targeting shoppers in an online shopping environment
    61.
    发明申请
    Targeting shoppers in an online shopping environment 审中-公开
    在线购物环境中定位购物者

    公开(公告)号：US20050096997A1

    公开(公告)日：2005-05-05

    申请号：US10699173

    申请日：2003-10-31

    申请人： Vivek Jain ,  Ravi Kothari

    发明人： Vivek Jain ,  Ravi Kothari

    IPC分类号： G06Q30/00 ,  G06F17/60

    CPC分类号： G06Q30/02 ,  G06Q30/0601

    摘要： Within an online shopping environment, a hosting server supports shoppers and merchants from whom the shoppers purchase goods or services. The hosting server enables an individual user to shop or browse the merchant sites and also enables a group of users to coordinate their shopping or browsing activities. A set of profiling tools build separate profiles based on individual and group shopper activity, as well as the interaction of an individual shopper with one or more groups of shoppers. A targeting tool uses the shopper profiles and information regarding previous promotions (if any) from a promotions library to make recommendations to individual shoppers and shopper groups based also on parameters specified by the merchant/s. The recommendations are directed to shoppers, in accordance with algorithms stored in a repository.

    摘要翻译： 在网络购物环境中，托管服务器支持购物者和购物者从中购买商品或服务的商家。 托管服务器使得个人用户能够购物或浏览商家站点，并且还使一组用户能够协调其购物或浏览活动。 一组分析工具基于个人和团体购物者活动以及个人购物者与一组或多组购物者的互动构建单独的配置文件。 目标工具使用购物者资料和关于促销图书馆以前促销（如果有的话）的信息，还可以根据商家指定的参数向个人购物者和购物者组提出建议。 根据存储在存储库中的算法，这些建议针对购物者。

    Method improving integrated circuit planarization during etchback
    62.
    发明授权
    Method improving integrated circuit planarization during etchback 失效

    公开(公告)号：US5496774A

    公开(公告)日：1996-03-05

    申请号：US363062

    申请日：1994-12-21

    申请人： Dipankar Pramanik ,  Vivek Jain ,  Milind G. Weling

    发明人： Dipankar Pramanik ,  Vivek Jain ,  Milind G. Weling

    IPC分类号： H01L21/768 ,  H01L21/44

    CPC分类号： H01L21/76819

    摘要： An integrated circuit fabrication method begins with semiconductor devices formed on a substrate. A patterned metal layer is deposited on the substrate to connect the semiconductor devices. A nitride layer is deposited over the metal layer and substrate. The nitride layer topography comprises hills located over metal regions and valleys located over non-metal regions. Spin-on-glass (SOG) is deposited over the nitride layer, thereby filling the valleys and covering the hills. The SOG layer and the nitride layer hills are etched back at substantially the same etch rate, using plasma etching, to form a planar surface. An oxide layer is then deposited over the planar surface to encapsulate the semiconductor devices, metal layer, nitride layer and SOG layer. Vias may then be etched through the oxide layer and the nitride layer to expose portions of the underlying metal layer and facilitate upper layer metal connections thereto. A second metal layer is deposited on the oxide layer and the fabrication process continues until the integrated circuit is complete.

    Planarization
    63.
    发明授权
    Planarization 失效
    平面化

    公开(公告)号：US5378318A

    公开(公告)日：1995-01-03

    申请号：US893616

    申请日：1992-06-05

    申请人： Milind Weling ,  Vivek Jain

    发明人： Milind Weling ,  Vivek Jain

    IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/00

    CPC分类号： H01L21/31116 ,  H01L21/76819

    摘要： A method for improved planarization of surface topographies encountered in semiconductor processing that involve the etch-back of exposed surfaces of an oxide of silicon and a spin-on-glass. The oxide of silicon is chosen to be oxygen-deficient and thus silicon-rich, with a spectroscopically-defined silicon richness coefficient CSR that is greater than 0, and preferably greater than 0.005. A fluorine-containing process gas such as CHF.sub.3 combined with one or more of CF.sub.4, C.sub.2 F.sub.6 and SF.sub.6 can be used in the etch chemistry. Sensitivity of the etch rate to certain parameters, such as the relative surface area of the exposed oxide of silicon and the fraction of fluorine present, is either reduced or eliminated. Improvement and better control of planarization is achieved by the process, resulting in a widening of the etch-back process window.

    摘要翻译： 一种用于改善在半导体处理中遇到的表面形貌的平面化的方法，其涉及硅的氧化物和旋涂玻璃的暴露表面的回蚀。 硅的氧化物选择为缺氧的，因此富含硅，其光谱定义的硅富集系数CSR大于0，优选大于0.005。 在蚀刻化学中可以使用与CF4，C2F6和SF6中的一种或多种组合的含氟工艺气体，例如CHF 3。 蚀刻速率对某些参数（例如暴露的硅的氧化物的相对表面积和存在的氟的分数）的敏感度被降低或消除。 通过该过程实现了平坦化的改进和更好的控制，导致了回蚀加工窗口的扩大。

    Method for making cusp-free anti-fuse structures
    65.
    发明授权
    Method for making cusp-free anti-fuse structures 失效
    制造无尖锐反熔丝结构的方法

    公开(公告)号：US5328865A

    公开(公告)日：1994-07-12

    申请号：US11084

    申请日：1993-01-29

    申请人： William J. Boardman ,  David P. Chan ,  Kuang-Yeh Chang ,  Calvin T. Gabriel ,  Vivek Jain ,  Subhash R. Nariani

    发明人： William J. Boardman ,  David P. Chan ,  Kuang-Yeh Chang ,  Calvin T. Gabriel ,  Vivek Jain ,  Subhash R. Nariani

    IPC分类号： H01L21/768 ,  H01L23/525 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L23/5252 ,  H01L21/76888 ,  H01L2924/0002

    摘要： A method for making an anti-fuse structure characterized by the steps of forming a conductive base layer; forming an anti-fuse layer over the base layer; patterning the anti-fuse layer to form an anti-fuse island; forming an insulating layer over the anti-fuse island; forming a via hole through the insulating layer to the anti-fuse island; forming a conductive connection layer over the insulating layer and within the via hole; and patterning the conductive connection layer to form a conductive contact to the anti-fuse island. Preferably, the anti-fuse island comprises amorphous silicon which can optionally be covered with a thin layer of a titanium-tungsten alloy.

    摘要翻译： 一种制造抗熔丝结构的方法，其特征在于形成导电基层的步骤; 在基层上形成抗熔丝层; 图案化抗熔丝层以形成抗熔丝岛; 在反熔丝岛上形成绝缘层; 形成通过所述绝缘层到所述反熔丝岛的通孔; 在所述绝缘层上并在所述通孔内形成导电连接层; 以及图案化所述导电连接层以形成与所述反熔丝岛的导电接触。 优选地，抗熔丝岛包括非晶硅，其可任选地被钛 - 钨合金的薄层覆盖。

    Method for robust real-time wireless industrial communication
    70.
    发明授权
    Method for robust real-time wireless industrial communication 有权
    强大的实时无线工业通信方法

    公开(公告)号：US09439194B2

    公开(公告)日：2016-09-06

    申请号：US14210864

    申请日：2014-03-14

    申请人： Robert Bosch GmbH

    发明人： Vivek Jain ,  Junseok Kim ,  Matthias Bauer ,  Gunther May

    IPC分类号： H04W4/00 ,  H04W72/04 ,  H04L5/00 ,  H04W84/18

    CPC分类号： H04W72/0453 ,  H04L5/00 ,  H04L5/0007 ,  H04L5/0037 ,  H04L5/0044 ,  H04L5/0048 ,  H04L27/2613 ,  H04L27/2656 ,  H04L27/2692 ,  H04W84/18

    摘要： Methods for operating real-time wireless networks enable robust medium access strategies for communicating nodes in the network. A given wireless channel is divided into several sub-carriers, with each node assigned to a subset of sub-carriers. A master wireless node uses different subsets of the sub-carriers to communication with two or more slave wireless nodes simultaneously. The method includes generation of preambles that are robust to interference and multipath conditions. The method also enables communication within a maximum predetermined latency bound.

    摘要翻译： 用于操作实时无线网络的方法支持用于在网络中通信节点的强大的媒体接入策略。 给定的无线信道被划分成几个子载波，其中每个节点分配给子载波子集。 主无线节点使用子载波的不同子集同时与两个或多个从属无线节点进行通信。 该方法包括产生对干扰和多径条件可靠的前导码。 该方法还使得能够在最大预定延迟范围内进行通信。