公开(公告)号：US5399533A

公开(公告)日：1995-03-21

申请号：US161642

申请日：1993-12-01

Applicant: Dipankar Pramanik ,  Vivek Jain ,  Milind Weling

Inventor： Dipankar Pramanik ,  Vivek Jain ,  Milind Weling

IPC: H01L21/768 ,  H01R ,  H01R4/64

CPC classification number: H01L21/76819

Abstract: An integrated circuit fabrication method begins with semiconductor devices formed on a substrate. A patterned metal layer is deposited on the substrate to connect the semiconductor devices. A nitride layer is deposited over the metal layer and substrate. The nitride layer topography comprises hills located over metal regions and valleys located over non-metal regions. Spin-on-glass (SOG) is deposited over the nitride layer, thereby filling the valleys and covering the hills. The SOG layer and the nitride layer hills are etched back at substantially the same etch rate, using plasma etching, to form a planar surface. An oxide layer is then deposited over the planar surface to encapsulate the semiconductor devices, metal layer, nitride layer and SOG layer. Vias may then be etched through the oxide layer and the nitride layer to expose portions of the underlying metal layer and facilitate upper layer metal connections thereto. A second metal layer is deposited on the oxide layer and the fabrication process continues until the integrated circuit is complete.

Abstract translation: 集成电路制造方法从形成在衬底上的半导体器件开始。 图案化的金属层沉积在衬底上以连接半导体器件。 氮化物层沉积在金属层和衬底上。 氮化物层形貌包括位于非金属区域上的金属区域和山谷之上的山丘。 旋转玻璃（SOG）沉积在氮化物层上，从而填充谷并覆盖山丘。 使用等离子体蚀刻以基本相同的蚀刻速率回蚀SOG层和氮化物层丘，以形成平坦表面。 然后在平面表面上沉积氧化物层以封装半导体器件，金属层，氮化物层和SOG层。 然后可以将通孔蚀刻通过氧化物层和氮化物层以暴露下面的金属层的部分，并促进与其的上层金属连接。 第二金属层沉积在氧化物层上，制造过程继续进行，直到集成电路完成。

公开(公告)号：US5522957A

公开(公告)日：1996-06-04

申请号：US171491

申请日：1993-12-22

Applicant: Milind Weling ,  Calvin T. Gabriel ,  Vivek Jain ,  Dipankar Pramanik

Inventor： Milind Weling ,  Calvin T. Gabriel ,  Vivek Jain ,  Dipankar Pramanik

IPC: H01J37/32 ,  H01L21/306

CPC classification number: H01J37/3244 ,  H01J37/32935 ,  Y10S148/162

Abstract: A method and apparatus for detecting the presence of gaseous impurities, notably oxygen, in a gas mixture that flows over an IC wafer in an etcher during the etching process. The method is based upon the discovery that the ratio of the etch rate of spin-on-glass material to the etch rate of other materials, such as plasma-enhanced chemical vapor deposition (PECVD oxide) materials, varies in a predictable manner with the amount of oxygen contaminating the gas mixture. The standard ratio, in the absence of oxygen, is determined for a given set of processing conditions by first etching an SOG wafer, then etching a PECVD oxide material wafer, measuring the amount of material etched in each case, and from that calculating the respective etch rates, and finally taking the ratio of the two calculated etch rates. This standard ratio is used as the benchmark for future tests. When a production run is to be conducted on a new material, the above procedure is repeated when the equipment is otherwise ready for the run, and the new calculated etch rate ratio is compared with the standard ratio. If they are substantially equal, this indicates a lack of oxygen contamination. If the ratio has changed, and other processing conditions have been taken into account (such as RF power and temperature), this indicates the presence of impurities in the gas mixture, and hence probably a leak in the system, or contamination of the gas source itself. In IC manufacturing, the production run is then typically stopped to correct the problem. Calibration data can be generated in advance to determine by how much to adjust the etching time, given a particular measured ratio that is not the same as the standard ratio. The system may be automatically controlled by a computer that calculates the corrected etching time based upon the measured ratio of the respective etch rates of SOG and the PECVD oxide material.

Abstract translation: 一种用于在蚀刻过程期间在蚀刻器中流过IC晶片的气体混合物中检测气态杂质（特别是氧）的存在的方法和装置。 该方法基于以下发现：旋涂玻璃材料的蚀刻速率与其它材料（诸如等离子体增强化学气相沉积（PECVD氧化物）材料）的蚀刻速率的比率以可预测的方式以 氧气混合物的污染量。 在不存在氧的情况下，通过首先蚀刻SOG晶片，然后蚀刻PECVD氧化物材料晶片，测量在每种情况下蚀刻的材料的量，并从计算相应的 蚀刻速率，最后得到两个计算的蚀刻速率的比值。 该标准比例被用作未来测试的基准。 当对新材料进行生产运行时，当设备准备运行时，重复上述步骤，并将新计算的蚀刻速率比与标准比率进行比较。 如果它们基本相同，则这表明缺乏氧气污染。 如果比例发生变化，并考虑了其他加工条件（如RF功率和温度），则表明气体混合物中存在杂质，因此可能是系统泄漏或气体源的污染 本身。 在IC制造中，通常停止生产运行以纠正问题。 可以预先产生校准数据，以确定调整蚀刻时间的程度，给定与标准比率不同的特定测量比。 该系统可以由计算机自动控制，该计算机基于SOG和PECVD氧化物材料的相应蚀刻速率的测量比来计算校正的蚀刻时间。

公开(公告)号：US5378318A

公开(公告)日：1995-01-03

申请号：US893616

申请日：1992-06-05

Applicant: Milind Weling ,  Vivek Jain

Inventor： Milind Weling ,  Vivek Jain

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/00

CPC classification number: H01L21/31116 ,  H01L21/76819

Abstract: A method for improved planarization of surface topographies encountered in semiconductor processing that involve the etch-back of exposed surfaces of an oxide of silicon and a spin-on-glass. The oxide of silicon is chosen to be oxygen-deficient and thus silicon-rich, with a spectroscopically-defined silicon richness coefficient CSR that is greater than 0, and preferably greater than 0.005. A fluorine-containing process gas such as CHF.sub.3 combined with one or more of CF.sub.4, C.sub.2 F.sub.6 and SF.sub.6 can be used in the etch chemistry. Sensitivity of the etch rate to certain parameters, such as the relative surface area of the exposed oxide of silicon and the fraction of fluorine present, is either reduced or eliminated. Improvement and better control of planarization is achieved by the process, resulting in a widening of the etch-back process window.

Abstract translation: 一种用于改善在半导体处理中遇到的表面形貌的平面化的方法，其涉及硅的氧化物和旋涂玻璃的暴露表面的回蚀。 硅的氧化物选择为缺氧的，因此富含硅，其光谱定义的硅富集系数CSR大于0，优选大于0.005。 在蚀刻化学中可以使用与CF4，C2F6和SF6中的一种或多种组合的含氟工艺气体，例如CHF 3。 蚀刻速率对某些参数（例如暴露的硅的氧化物的相对表面积和存在的氟的分数）的敏感度被降低或消除。 通过该过程实现了平坦化的改进和更好的控制，导致了回蚀加工窗口的扩大。

公开(公告)号：US06410440B1

公开(公告)日：2002-06-25

申请号：US09305977

申请日：1999-05-05

Applicant: Charles F. Drill ,  Milind Weling

Inventor： Charles F. Drill ,  Milind Weling

IPC: H01L21302

CPC classification number: H01L21/3212 ,  B24B37/042 ,  H01L21/31053

Abstract: A method of using a gaseous environment providing improved control of CMP process. In one embodiment, the method comprises several steps. One step involves placing a semiconductor wafer onto a polishing pad of a CMP machine. A subsequent step dispenses a slurry onto the polishing pad. Another step provides a blanket of gas that displaces the ambient atmosphere surrounding the semiconductor wafer. In another step, the blanket of gas is maintained around the semiconductor wafer during the CMP operation.

Abstract translation: 一种使用气体环境提供改进的CMP工艺控制的方法。 在一个实施例中，该方法包括几个步骤。 一步涉及将半导体晶片放置在CMP机器的抛光垫上。 随后的步骤将浆料分配到抛光垫上。 另一个步骤提供了一个气体覆盖物，其覆盖半导体晶片周围的环境大气。 在另一步骤中，在CMP操作期间，气体保护层保持在半导体晶片周围。

公开(公告)号：US06353261B1

公开(公告)日：2002-03-05

申请号：US09303891

申请日：1999-05-03

Applicant: Milind Weling

Inventor： Milind Weling

IPC: H01L2348

CPC classification number: H01L23/522 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An apparatus for reducing interconnect resistance using optimized trench geometry. One embodiment comprises an interconnect line and an interconnect well. The interconnect line, comprised of a conductive material, has a depth and exists in a first circuit layer of a multilayered Integrated Circuit (IC). The interconnect well is coupled to the interconnect line and is insulated from other conductive materials in the first circuit layer, and in the plurality of subsequent adjacent layers. The interconnect well has a depth in said multilayered IC that exceeds said depth of said interconnect line.

Abstract translation: 一种使用优化沟槽几何形状降低互连电阻的设备。 一个实施例包括互连线和互连阱。 由导电材料构成的互连线具有深度并存在于多层集成电路（IC）的第一电路层中。 互连阱耦合到互连线，并且与第一电路层中的其它导电材料以及多个随后的相邻层绝缘。 互连阱在所述多层IC中具有超过所述互连线的所述深度的深度。

公开(公告)号：US06319796B1

公开(公告)日：2001-11-20

申请号：US09377043

申请日：1999-08-18

Applicant: Olivier Laparra ,  Ramiro Solis ,  Hunter Brugge ,  Michela S. Love ,  Bijan Moslehi ,  Milind Weling

Inventor： Olivier Laparra ,  Ramiro Solis ,  Hunter Brugge ,  Michela S. Love ,  Bijan Moslehi ,  Milind Weling

IPC: H01L2176

CPC classification number: H01L21/76224 ,  Y10S148/05

Abstract: Disclosed are techniques to provide an integrated circuit, including the provision of improved integrated circuit isolation structures. The techniques include forming a number of trenches in an integrated circuit substrate to define a number of substrate regions that are to be electrically isolated from one another. A dielectric material is deposited in the trenches by exposure to a high density plasma having a first deposition-to-etch ratio. The high density plasma is adjusted to a second deposition-to-etch ratio greater than the first ratio to accumulate the dielectric material on the substrate after at least partially filling the trenches. A portion of the dielectric material is removed to planarize the workpiece. A number of components, such as insulated gate field effect transistors, may be subsequently formed in the substrate regions between the trenches.

Abstract translation: 公开了提供集成电路的技术，包括提供改进的集成电路隔离结构。 这些技术包括在集成电路衬底中形成多个沟槽以限定要彼此电绝缘的多个衬底区域。 通过暴露于具有第一沉积到蚀刻比的高密度等离子体，在沟槽中沉积电介质材料。 将高密度等离子体调整到大于第一比率的第二沉积蚀刻比，以在至少部分地填充沟槽之后在基板上积累电介质材料。 去除介电材料的一部分以使工件平坦化。 可以随后在沟槽之间的衬底区域中形成多个组件，例如绝缘栅场效应晶体管。

公开(公告)号：US06193860B1

公开(公告)日：2001-02-27

申请号：US09298629

申请日：1999-04-23

Applicant: Milind Weling

Inventor： Milind Weling

IPC: C25B904

CPC classification number: C25D17/12 ,  C25D7/12 ,  C25D17/001 ,  C25D21/12

Abstract: An apparatus for optimizing electrical currents to improve copper plating uniformity on a semiconductor wafer is disclosed. The use of multiple anodes of the embodiment provides for variable electrical currents to the semiconductor wafer, the variable feature of the variable electrical currents compensating for non-uniform electroplating characteristics.

Abstract translation: 公开了一种用于优化电流以提高半导体晶片上的镀铜均匀性的装置。 本实施例的多个阳极的使用提供了对半导体晶片的可变电流，可变电流的可变特征补偿了不均匀的电镀特性。

公开(公告)号：US6022265A

公开(公告)日：2000-02-08

申请号：US100276

申请日：1998-06-19

Applicant: Charles F. Drill ,  Calvin Gabriel ,  Milind Weling ,  Richard Russ ,  David E. Henderson

Inventor： Charles F. Drill ,  Calvin Gabriel ,  Milind Weling ,  Richard Russ ,  David E. Henderson

IPC: B24B53/007 ,  B24B53/013 ,  B24B53/017 ,  B24B1/00

CPC classification number: B24B53/017 ,  B24B53/013

Abstract: A complementary conditioning system for use in chemical mechanical polishing (CMP). The present invention functions with a CMP machine adapted for polishing a semiconductor wafer having tungsten components fabricated thereon. A polishing pad is mounted on the CMP machine. The polishing pad has a polishing surface configured for polishing the semiconductor wafer and its tungsten components. The performance of the polishing surface is characterized by a polishing efficiency. A complementary end-effector is mounted on the CMP machine. The complementary end-effector is adapted to chemically complement the tungsten components on the semiconductor wafer. The complementary end-effector is further adapted to contact the polishing surface and improve the polishing efficiency by chemically enhancing the polishing surface, thereby obtaining a more efficient removal rate for the chemical mechanical polishing.

Abstract translation: 用于化学机械抛光（CMP）的补充调理系统。 本发明与适用于抛光其上制造有钨成分的半导体晶片的CMP机器相结合。 抛光垫安装在CMP机器上。 抛光垫具有被配置用于抛光半导体晶片及其钨组分的抛光表面。 研磨表面的性能的特征在于抛光效率。 互补的末端执行器安装在CMP机器上。 互补末端执行器适于化学补充半导体晶片上的钨成分。 补充的末端执行器还适于接触抛光表面并且通过化学增强抛光表面来提高抛光效率，从而获得用于化学机械抛光的更有效的去除速率。

公开(公告)号：US08679981B1

公开(公告)日：2014-03-25

申请号：US12943808

申请日：2010-11-10

Applicant: Milind Weling ,  Judy Huckabay ,  Abdurrahman Sezginer

Inventor： Milind Weling ,  Judy Huckabay ,  Abdurrahman Sezginer

IPC: H01L21/302

CPC classification number: H01L21/033 ,  G03F1/00

Abstract: Various embodiments of the invention provide systems and methods for semiconductor device fabrication and generation of photomasks for patterning a target layout of line features and large features. Embodiments of the invention are directed towards systems and methods using self-aligned double pattern to define the target layout of line features and large features.

Abstract translation: 本发明的各种实施例提供用于半导体器件制造和生成用于图案化线特征和大特征的目标布局的光掩模的系统和方法。 本发明的实施例涉及使用自对准双重图案来定义线特征和大特征的目标布局的系统和方法。

公开(公告)号：US07018282B1

公开(公告)日：2006-03-28

申请号：US08824633

申请日：1997-03-27

Applicant: Charles Franklin Drill ,  Milind Weling

Inventor： Charles Franklin Drill ,  Milind Weling

IPC: B24D11/00

CPC classification number: B24B37/20 ,  B24B37/042 ,  B24B37/26

Abstract: The present invention comprises a customized polishing pad for use in a wafer polishing machine. The polishing pad of the present invention includes a polishing surface integral with the polishing pad. The polishing surface is adapted to frictionally contact a wafer in the polishing machine, thereby polishing the wafer. The polishing surface of the polishing pad includes at least two areas, where each area is adapted to frictionally contact the wafer and achieve a polishing effect specific for that area. A customized polishing effect is achieved by the polishing pad of the present invention when the wafer is selectively moved frictionally against the at least two areas by the wafer polishing machine.