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    VEHICLE STEERING CONTROL SYSTEM
    61.
    发明申请
    VEHICLE STEERING CONTROL SYSTEM 审中-公开
    车辆转向控制系统

    公开(公告)号：US20080059026A1

    公开(公告)日：2008-03-06

    申请号：US11846206

    申请日：2007-08-28

    申请人： Satoru Akiyama

    发明人： Satoru Akiyama

    IPC分类号： B62D6/00

    CPC分类号： B62D5/008 ,  B62D5/0472 ,  B62D6/008

    摘要： A vehicle steering control system is provided in which a power steering mechanism provides adequate assistance to a steering reactive force even when a steering angle correction mechanism is actuated in addition to a vehicle operator's steering operation, thereby maintaining a feeling of stable steering without causing the operator to feel unusual. Considering a correction amount of front wheel steering angle provided by an auxiliary steering control section, a power steering control section corrects an assist current from an assist current map prepared based on a vehicle speed and a steering torque, the correction of which is made by converting the correction amount of front wheel steering angle into a correction amount of power steering electric motor current to correct the assist current, or into a vehicle speed correction amount to correct the vehicle speed.

    摘要翻译： 提供了一种车辆转向控制系统，其中即使在除了车辆操作者的转向操作之外还可以启动转向角校正机构的情况下，动力转向机构向转向反作用力提供足够的辅助，从而保持转向稳定的感觉，而不会使操作者 感觉不寻常 考虑到由辅助转向控制部提供的前轮转向角的校正量，动力转向控制部根据基于车速和转向转矩而制作的辅助电流映像来校正辅助电流，其通过转换进行校正 将前轮舵角的修正量变换为动力转向电动机电流的校正量，以校正辅助电流，或者改变为车速校正量以校正车速。

    Semiconductor device with multi-bank DRAM and cache memory
    62.
    发明申请
    Semiconductor device with multi-bank DRAM and cache memory 审中-公开
    具有多组DRAM和高速缓冲存储器的半导体器件

    公开(公告)号：US20050111284A1

    公开(公告)日：2005-05-26

    申请号：US11019269

    申请日：2004-12-23

    申请人： Satoru Akiyama ,  Yusuke Kanno ,  Takao Watanabe

    发明人： Satoru Akiyama ,  Yusuke Kanno ,  Takao Watanabe

    IPC分类号： G06F12/08 ,  G11C11/401 ,  G11C11/403 ,  G11C11/406 ,  G11C11/41 ,  G11C7/00

    CPC分类号： G11C11/40615 ,  G06F12/0893 ,  G06F2212/3042 ,  G11C11/406 ,  G11C2207/2245

    摘要： To provide means that can hide refresh operations even when the data width of a cache line differs from that of the external data bus in a memory that uses a cache memory and a DRAM consisting of a plurality of banks. A semiconductor device consisting of a plurality of memory banks BANK0 to BANK127, each consisting of a plurality of memory cells, as well as a cache memory CACHEMEM used to retain information read from the plurality of memory banks. The cache memory CACHEMEM consists of a plurality of entries, each having a data memory DATAMEM and a tag memory TAGMEM. The data memory DATAMEM consists of a plurality of sub lines DATA0 to DATA3 and the tag memory TAGMEM Consists of a plurality of valid bits V0 to V3 and a plurality of dirty bits D0 to D3. It is possible to realize a memory with excellent operability, causing no refresh operation to delay external accesses. In other words, it is possible to realize a memory compatible with an SRAM in which refresh operations are hidden from external.

    摘要翻译： 即使当高速缓存行的数据宽度与使用高速缓冲存储器的存储器和由多个存储体组成的DRAM的外部数据总线的数据宽度不同时，也可以隐藏刷新操作。 由多个存储器组BANK 0至BANK 127组成的半导体器件，每个存储器组由多个存储器单元组成，以及用于保持从多个存储体读取的信息的高速缓冲存储器CACHEMEM。 高速缓冲存储器CACHEMEM由多个条目组成，每个条目具有数据存储器DATAMEM和标签存储器TAGMEM。 数据存储器DATAMEM由多条子线DATA 0至数据3组成，标签存储器TAGMEM由多个有效位V 0至V 3和多个脏位D 0至D 3组成。可以实现 具有优异可操作性的存储器，不会引起刷新操作来延迟外部访问。 换句话说，可以实现与其中刷新操作被外部隐藏的SRAM兼容的存储器。

    Image pickup apparatus
    64.
    发明授权
    Image pickup apparatus 有权
    摄像设备

    公开(公告)号：US08692922B2

    公开(公告)日：2014-04-08

    申请号：US13315393

    申请日：2011-12-09

    申请人： Satoru Akiyama

    发明人： Satoru Akiyama

    IPC分类号： H04N5/222 ,  H04N5/225

    CPC分类号： H04N5/2259 ,  G03B17/18 ,  G03B2217/18 ,  H04N5/2252

    摘要： An image pickup apparatus capable of giving a shooter the same rotary operation feeling regardless of the rotating direction, and displaying an erect image to a shooter at all times. A two-axis hinge is provided with a first bearing that supports a display unit rotatably in right and left directions and a second bearing that supports the display unit in rotated states rotatably so as to direct the screen to front and rear sides. A first axial rotation detector detects the rotation of the display unit by the first bearing. A second axial rotation detector detects the rotation of the display unit in the rotated states by the second bearing to direct the screen to the front and rear sides. A control unit switches display orientation of an image displayed on the display unit based on detection results from the first and second axial rotation detectors.

    摘要翻译： 一种能够给予射手相同的旋转操作感觉而不管旋转方向如何的图像拾取装置，并且始终将直立图像显示给射手。 双轴铰链设置有第一轴承，该第一轴承可在左右方向上以可旋转的方式支撑显示单元;以及第二轴承，其可转动地支撑显示单元，以将屏幕导向前后侧。 第一轴向旋转检测器通过第一轴承检测显示单元的旋转。 第二轴向旋转检测器通过第二轴承检测显示单元在旋转状态下的旋转，以将屏幕引导到前侧和后侧。 控制单元基于来自第一和第二轴向旋转检测器的检测结果来切换显示在显示单元上的图像的显示方位。

    Steering control system for vehicle
    65.
    发明授权
    Steering control system for vehicle 有权
    车辆转向控制系统

    公开(公告)号：US08234044B2

    公开(公告)日：2012-07-31

    申请号：US13052503

    申请日：2011-03-21

    申请人： Koji Matsuno ,  Satoru Akiyama ,  Shinji Matsushita ,  Shiro Ezoe ,  Masaru Kogure ,  Hajime Oyama

    发明人： Koji Matsuno ,  Satoru Akiyama ,  Shinji Matsushita ,  Shiro Ezoe ,  Masaru Kogure ,  Hajime Oyama

    IPC分类号： B62D6/00

    CPC分类号： B62D6/003 ,  B62D5/008

    摘要： A steering control section has a first steering angle correction amount calculating section, a second steering angle correction amount calculating section, and a motor rotational angle calculating section. The first correction amount calculating section calculates a first correction amount based on a vehicle speed and an actual steering wheel angle. The second correction amount calculating section calculates a second correction amount through multiplying a control gain corresponding to the vehicle speed with a value calculated by low-pass filtering a differential value of steering wheel angle. The motor rotational angle calculating section calculates a motor rotational angle corresponding to the value adding the first and second steering angle correction amount, and outputs it to a motor driving section so as to drive an electric motor for correcting the steering angle. Thereby, an unstable vehicle behavior due to a resonance of a yaw motion caused in the steering operation can be suppressed.

    摘要翻译： 转向控制部具有第一转向角修正量计算部，第二转向角修正量计算部和电动机转动角计算部。 第一校正量计算部基于车速和实际方向盘角度来计算第一校正量。 第二校正量计算部分通过将与车速相对应的控制增益乘以通过对方向盘角度的差分值进行低通滤波而计算的值来计算第二校正量。 马达旋转角度计算部分计算与增加第一和第二转向角校正量的值相对应的马达旋转角度，并将其输出到马达驱动部分，以驱动用于校正转向角的电动马达。 由此，可以抑制由于在转向操作中引起的偏航运动的共振引起的不稳定的车辆行为。

    IMAGING APPARATUS
    66.
    发明申请
    IMAGING APPARATUS 有权
    成像设备

    公开(公告)号：US20110109784A1

    公开(公告)日：2011-05-12

    申请号：US12941924

    申请日：2010-11-08

    申请人： Satoru Akiyama

    发明人： Satoru Akiyama

    IPC分类号： H04N5/225

    CPC分类号： H04N5/23293 ,  H04N5/2251 ,  H04N5/772 ,  H04N5/907

    摘要： An imaging apparatus includes a display unit capable of being displaced between a non use state and a use state in such a manner that a display surface displaying an image of a subject is directed at least to the subject or a user in the use state, and a display control unit that inverts a direction in a vertical direction of the image of the subject displayed on the display surface in response to an operation on an operation member when the display unit is in the use state and cancels the inversion when the display unit is in the non use state.

    摘要翻译： 一种成像装置包括：显示单元，其能够以非使用状态和使用状态之间的位移，使得显示被摄体的图像的显示表面至少指向对象或使用状态下的用户;以及 显示控制单元，当显示单元处于使用状态时，响应于对操作构件的操作而反转显示在显示表面上的被摄体的图像的垂直方向的方向，并且当显示单元是 在非使用状态。

    Semiconductor device having plural dram memory cells and a logic circuit
    68.
    发明授权
    Semiconductor device having plural dram memory cells and a logic circuit 失效
    具有多个显影存储单元和逻辑电路的半导体器件

    公开(公告)号：US07408218B2

    公开(公告)日：2008-08-05

    申请号：US10488401

    申请日：2001-12-14

    申请人： Satoru Akiyama ,  Takao Watanabe ,  Yuichi Matsui ,  Masahiko Hiratani

    发明人： Satoru Akiyama ,  Takao Watanabe ,  Yuichi Matsui ,  Masahiko Hiratani

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10852 ,  H01L23/5223 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A memory cell capacitor (C3) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M3) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher integration is achievable by forming the capacitor using a high dielectric constant material and disposing it above a wiring layer in which bit lines (BL) are formed. In addition, using 2T cells makes it possible to provide a sufficient signal amount even when letting them operate with a low voltage. By commonizing the processes for fabricating capacitors in analog (ANALOG) and memory (MEM), it is possible to realize a semiconductor integrated circuit with the logic, analog and memory mounted together on one chip at low costs.

    摘要翻译： DRAM的存储单元电容器（C 3）通过使用MIM电容器形成，该MIM电容器使用与逻辑电路（LOGIC）内的金属布线相同的层（M 3）的金属布线，从而使能 降低工艺成本。 通过使用高介电常数材料形成电容器并将其布置在其中形成位线（BL）的布线层上方，可以实现更高的积分。 此外，使用2T电池使得即使当它们以低电压工作时也可以提供足够的信号量。 通过对模拟（ANALOG）和存储器（MEM）中制造电容器的工艺进行通用化，可以以低成本在一个芯片上实现将逻辑，模拟和存储器安装在一起的半导体集成电路。

    Steering control system for vehicle
    69.
    发明申请
    Steering control system for vehicle 有权
    车辆转向控制系统

    公开(公告)号：US20070039775A1

    公开(公告)日：2007-02-22

    申请号：US11477347

    申请日：2006-06-30

    申请人： Koji Matsuno ,  Satoru Akiyama ,  Shinji Matsushita ,  Shiro Ezoe ,  Masaru Kogure ,  Hajime Oyama

    发明人： Koji Matsuno ,  Satoru Akiyama ,  Shinji Matsushita ,  Shiro Ezoe ,  Masaru Kogure ,  Hajime Oyama

    IPC分类号： B62D5/04

    CPC分类号： B62D6/003 ,  B62D5/008

    摘要： A steering control section has a first steering angle correction amount calculating section, a second steering angle correction amount calculating section, and a motor rotational angle calculating section. The first correction amount calculating section calculates a first correction amount based on a vehicle speed and an actual steering wheel angle. The second correction amount calculating section calculates a second correction amount through multiplying a control gain corresponding to the vehicle speed with a value calculated by low-pass filtering a differential value of steering wheel angle. The motor rotational angle calculating section calculates a motor rotational angle corresponding to the value adding the first and second steering angle correction amount, and outputs it to a motor driving section so as to drive an electric motor for correcting the steering angle. Thereby, an unstable vehicle behavior due to a resonance of a yaw motion caused in the steering operation can be suppressed.

    摘要翻译： 转向控制部具有第一转向角修正量计算部，第二转向角修正量计算部和电动机转动角计算部。 第一校正量计算部基于车速和实际方向盘角度来计算第一校正量。 第二校正量计算部分通过将与车速相对应的控制增益乘以通过对方向盘角度的差分值进行低通滤波而计算的值来计算第二校正量。 马达旋转角度计算部分计算与增加第一和第二转向角校正量的值相对应的马达旋转角度，并将其输出到马达驱动部分，以驱动用于校正转向角的电动马达。 由此，可以抑制由于在转向操作中引起的偏航运动的共振引起的不稳定的车辆行为。

    Semiconductor device
    70.
    发明申请
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US20050180243A1

    公开(公告)日：2005-08-18

    申请号：US11105377

    申请日：2005-04-14

    申请人： Takao Watanabe ,  Hiroyuki Mizuno ,  Satoru Akiyama

    发明人： Takao Watanabe ,  Hiroyuki Mizuno ,  Satoru Akiyama

    IPC分类号： G11C11/403 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/02 ,  G11C11/405 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4076

    CPC分类号： G11C7/222 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/406 ,  G11C11/4076

    摘要： A memory includes first circuit RFPDRAM including memory cells and operating in response to first clock signal, second circuit and third circuit coupled with first circuit and bus coupling first circuit to second and third circuits. The second circuit outputs in response to second clock signal, first address signal to first circuit. The third circuit outputs in response to third clock signal, second address signal to first circuit. The first circuit includes refresh control circuit executing refresh operation for memory cells in response to fourth clock signal and address latch for storing first or second address signal in response to first clock signal. The first clock signal has frequency equal to or more than sum of frequencies respectively of second, third, and fourth clock signals.

    摘要翻译： 存储器包括包括存储器单元的第一电路RFPDRAM和响应于第一时钟信号，第二电路和与第一电路耦合的第三电路和第一电路耦合到第二和第三电路的总线耦合。 第二电路响应于第二时钟信号输出第一地址信号到第一电路。 第三电路响应于第三时钟信号输出第二地址信号到第一电路。 第一电路包括响应于第四时钟信号而对存储器单元执行刷新操作的刷新控制电路和响应于第一时钟信号存储第一或第二地址信号的地址锁存器。 第一时钟信号的频率分别等于或大于第二，第三和第四时钟信号的频率之和。