公开(公告)号：US09099465B2

公开(公告)日：2015-08-04

申请号：US14053531

申请日：2013-10-14

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L21/70 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76879 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Metal interconnections are formed in an integrated circuit by forming a wide trench in a dielectric layer. A dielectric fin of a second dielectric material is formed in the trench. Conductive plugs and metal lines are formed on both sides of the fin.

Abstract translation: 通过在电介质层中形成宽的沟槽，在集成电路中形成金属互连。 在沟槽中形成第二电介质材料的绝缘片。 导电插头和金属线形成在鳍的两侧。

公开(公告)号：US20150162277A1

公开(公告)日：2015-06-11

申请号：US14098286

申请日：2013-12-05

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Yann Mignot ,  Lawrence A. Clevenger ,  Carl Radens ,  Richard Stephen Wise ,  Yiheng Xu ,  Yannick Loquet ,  Hsueh-Chung Chen

IPC: H01L23/528 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/0217 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect structure incorporates air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of an air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the air gap is used as an insulator between adjacent metal lines, while a ULK film is retained to insulate vias. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.

Abstract translation: 在高性能集成电路中用作层间电介质的超低k电介质材料容易在结构上不稳定。 这种材料的杨氏模量降低，导致孔隙率，差的膜强度，开裂和空隙。 一种替代的双镶嵌互连结构将气隙结合到高模量介电材料中以保持结构稳定性，同时减小相邻纳米线之间的电容。 结合k = 1.0的气隙补偿使用介电常数大于典型的超低k（ULK）介电值约2.2的介电常数的较高模量的膜。 含有气隙的较高模量的膜用作相邻金属线之间的绝缘体，同时保留ULK膜以绝热通孔。 因此，两个相邻金属线之间的电介质层形成ULK /高模量介电双层。

公开(公告)号：US20150115401A1

公开(公告)日：2015-04-30

申请号：US14068198

申请日：2013-10-31

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Edem Wornyo

IPC: H01L49/02 ,  H01L21/3105 ,  H01L21/02

CPC classification number: H01L27/016 ,  H01L21/31053 ,  H01L21/3212 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/5252 ,  H01L23/5256 ,  H01L28/20 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A sequence of semiconductor processing steps permits formation of both vertical and horizontal nanometer-scale serpentine resistors and parallel plate capacitors within a common structure. The method of fabricating such a structure cleverly takes advantage of a CMP process non-uniformity in which the CMP polish rate of an insulating material varies according to a certain underlying topography. By establishing such topography underneath a layer of the insulating material, different film thicknesses of the insulator can be created in different areas by leveraging differential polish rates, thereby avoiding the use of a lithography mask. In one embodiment, a plurality of resistors and capacitors can be formed as a compact integrated structure within a common dielectric block, using a process that requires only two mask layers. The resistors and capacitors thus formed as a set of integrated circuit elements are suitable for use as microelectronic fuses and antifuses, respectively, to protect underlying microelectronic circuits.

Abstract translation: 半导体处理步骤的顺序允许在公共结构内形成垂直和水平的纳米级蛇形电阻器和平行板电容器。 制造这种结构的方法巧妙地利用CMP工艺不均匀性，其中绝缘材料的CMP抛光速率根据某些基础形貌而变化。 通过在绝缘材料层之下建立这样的形貌，可以通过利用差分抛光速率在不同的区域产生绝缘体的不同膜厚度，从而避免使用光刻掩模。 在一个实施例中，使用仅需要两个掩模层的工艺，可以在公共介电块内形成多个电阻器和电容器作为紧凑的集成结构。 这样形成为一组集成电路元件的电阻器和电容器分别适合用作微电子熔丝和反熔丝，以保护下面的微电子电路。

公开(公告)号：US20150096591A1

公开(公告)日：2015-04-09

申请号：US14047144

申请日：2013-10-07

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L21/67

CPC classification number: H01L21/02057 ,  B08B3/08 ,  B08B3/12 ,  H01L21/67028 ,  H01L21/67046

Abstract: A brush-cleaning apparatus is disclosed for use in cleaning a semiconductor wafer after polishing. Embodiments of the brush-cleaning apparatus implemented with a multi-branch chemical dispensing unit are applied beneficially to clean semiconductor wafers, post-polish, using a hybrid cleaning method. An exemplary hybrid cleaning method employs a two-chemical sequence in which first and second chemical treatment modules are separate from one another, and are followed by a pH-neutralizing-rinse that occurs in a treatment module separate from the first and second chemical treatment modules. Implementation of such hybrid methods is facilitated by the multi-branch chemical dispensing unit, which provides separate chemical lines to different chemical treatment modules, and dispenses chemical to at least four different areas of each wafer during single-wafer processing in an upright orientation. The multi-branch chemical dispensing unit provides a flexible, modular building block for constructing various equipment configurations that use multiple chemical treatments and/or pH neutralization steps.

Abstract translation: 公开了用于清洁抛光后的半导体晶片的刷子清洁装置。 使用多分支化学分配单元实施的刷子清洁装置的实施例有利地应用混合清洗方法来清洁半导体晶片，后抛光。 示例性的混合清洁方法采用其中第一和第二化学处理组件彼此分离的双化学序列，然后是在与第一和第二化学处理模块分开的处理模块中发生的pH中和漂洗 。 这种混合方法的实现通过多分支化学分配单元来实现，该分支化学分配单元向不同的化学处理模块提供单独的化学品流，并且在直立取向的单晶片处理期间将化学品分配给每个晶片的至少四个不同区域。 多分支化学分配单元提供了一种灵活的模块化构建块，用于构建使用多种化学处理和/或pH中和步骤的各种设备配置。

公开(公告)号：US08889506B1

公开(公告)日：2014-11-18

申请号：US13931737

申请日：2013-06-28

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Edem Wornyo

IPC: H01L29/94 ,  H01L31/062 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/32051 ,  H01L21/76844 ,  H01L21/7685 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/53295 ,  H01L29/66795 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit die includes a semiconductor substrate, a first dielectric layer on the substrate, and a second dielectric layer on the first dielectric layer. Trenches are formed in the first and second dielectric layers. Metal interconnection tracks are formed on sidewalls of the trench on the exposed portions of the second dielectric layer.

Abstract translation: 集成电路管芯包括半导体衬底，衬底上的第一介电层和第一介电层上的第二电介质层。 沟槽形成在第一和第二电介质层中。 金属互连轨道形成在第二电介质层的暴露部分上的沟槽的侧壁上。

公开(公告)号：US08859350B2

公开(公告)日：2014-10-14

申请号：US14157947

申请日：2014-01-17

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John H. Zhang ,  Yiheng Xu ,  Carl Radens ,  Lawrence A. Clevenger

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/778 ,  H01L27/12 ,  H01L21/84 ,  H01L29/165

CPC classification number: H01L29/66666 ,  H01L21/28008 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/7781

Abstract: A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority of the source region as well as a majority of the drain region and the entire gate electrode.

公开(公告)号：US08829670B1

公开(公告)日：2014-09-09

申请号：US13931688

申请日：2013-06-28

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Edem Wornyo

IPC: H01L23/34 ,  H01L21/50 ,  H01L21/44 ,  H01L23/46 ,  H01L23/473 ,  H01L21/48

CPC classification number: H01L23/473 ,  H01L21/4871 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/13011 ,  H01L2224/13147 ,  H01L2224/13194 ,  H01L2224/14051 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17519 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/00014

Abstract: The present disclosure is directed to a device that includes a first substrate having a first plurality of hollow pillars on the first substrate and a first plurality of channels in the first substrate coupled to the first plurality of hollow pillars. The device includes a second substrate attached to the first substrate, the second substrate having a second plurality of hollow pillars on the second substrate and a second plurality of channels in the second substrate coupled to the second plurality of hollow pillars, the first plurality of hollow pillars being coupled to the second plurality of hollow pillars to allow a fluid medium to move through the substrate to cool the first substrate and the second substrate.

Abstract translation: 本公开涉及一种装置，其包括在第一基板上具有第一多个中空柱的第一基板和耦合到第一多个空心支柱的第一基板中的第一多个通道。 该装置包括附接到第一基板的第二基板，第二基板在第二基板上具有第二多个中空支柱，而第二基板中的第二多个通道联接到第二多个中空支柱，第一多个中空 支柱联接到第二多个中空柱以允许流体介质移动通过基板以冷却第一基板和第二基板。

公开(公告)号：US20140084481A1

公开(公告)日：2014-03-27

申请号：US13629411

申请日：2012-09-27

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76834 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A plurality of metal tracks are formed in a plurality of intermetal dielectric layers stacked in an integrated circuit die. Thin protective dielectric layers are formed around the metal tracks. The protective dielectric layers act as a hard mask to define contact vias between metal tracks in the intermetal dielectric layers.

Abstract translation: 在集成电路管芯中层叠的多个金属间电介质层中形成多个金属轨道。 在金属轨道周围形成薄的保护电介质层。 保护性介电层用作硬掩模以限定金属轨道在金属间电介质层中的接触通孔。

公开(公告)号：US12211853B2

公开(公告)日：2025-01-28

申请号：US18326841

申请日：2023-05-31

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. Zhang

IPC: H01L27/12 ,  H01L21/266 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00 ,  H10B20/00

Abstract: Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

公开(公告)号：US11664415B2

公开(公告)日：2023-05-30

申请号：US17373586

申请日：2021-07-12

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. Zhang

IPC: H01L21/02 ,  H01L21/28 ,  H01L49/02 ,  H01L27/108 ,  H01L27/11507

CPC classification number: H01L28/56 ,  H01L21/02197 ,  H01L27/108 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/60 ,  H01L28/65 ,  H01L29/40111

Abstract: An interconnect structure for use in coupling transistors in an integrated circuit is disclosed, including various configurations in which ferroelectric capacitors exhibiting negative capacitance are coupled in series with dielectric capacitors. In one embodiment, the negative capacitor includes a dielectric/ferroelectric bi-layer. When a negative capacitor is electrically coupled in series with a conventional dielectric capacitor, the series combination behaves like a stable ferroelectric capacitor for which the overall capacitance can be measured experimentally, and tuned to a desired value. The composite capacitance of a dielectric capacitor and a ferroelectric capacitor having negative capacitance coupled in series is, in theory, infinite, and in practice, very large. A series combination of positive and negative capacitors within a microelectronic interconnect structure can be used to make high capacity DRAM memory cells.