公开(公告)号：US20160225676A1

公开(公告)日：2016-08-04

申请号：US14608815

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Jody A. Fronheiser

IPC: H01L21/84 ,  H01L21/8238 ,  H01L21/308 ,  H01L21/762 ,  H01L29/165 ,  H01L21/02

CPC classification number: H01L21/845 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/76264 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/165

Abstract: One illustrative method disclosed herein includes, among other things, forming a composite fin structure that is comprised of a first germanium-containing semiconductor material having a first concentration of germanium and a tensile-strained second semiconductor material (having a lesser germanium concentration) positioned on the first germanium-containing semiconductor material and performing a thermal anneal process to convert the first germanium-containing semiconductor material portion of the composite fin structure into a germanium-containing oxide isolation region positioned under the second semiconductor material that is a tensile-strained final fin for an NMOS FinFET device.

Abstract translation: 本文公开的一种说明性方法包括形成复合翅片结构，该复合翅片结构由具有第一锗浓度的第一含锗半导体材料和位于第一锗浓度的拉伸应变第二半导体材料（具有较小的锗浓度）组成 第一含锗半导体材料，并且进行热退火工艺以将复合翅片结构的第一含锗半导体材料部分转换成位于第二半导体材料下方的含锗氧化物隔离区域，该第一半导体材料是拉伸应变末端鳍 用于NMOS FinFET器件。

公开(公告)号：US09406803B2

公开(公告)日：2016-08-02

申请号：US14676239

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Jody A. Fronheiser ,  Murat Kerem Akarvardar ,  Steven Bentley

IPC: H01L21/326 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/161 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L29/7851 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/18 ,  H01L29/161

Abstract: A method includes forming at least one fin on a semiconductor substrate. A silicon alloy material is formed on the fin and on exposed surface portions of the substrate. A thermal process is performed to define a silicon alloy fin from the silicon alloy material and the fin and to define silicon alloy surface portions from the silicon alloy material and the exposed surface portions of the substrate. A semiconductor device includes a substrate, a fin defined on the substrate, the fin comprising a silicon alloy and having a substantially vertical sidewall, and silicon alloy surface portions on the substrate adjacent the fin.

Abstract translation: 一种方法包括在半导体衬底上形成至少一个翅片。 在所述散热片和所述基板的暴露的表面部分上形成硅合金材料。 执行热处理以从硅合金材料和翅片限定硅合金翅片，并且从硅合金材料和基底的暴露表面部分限定硅合金表面部分。 半导体器件包括衬底，限定在衬底上的鳍，鳍包括硅合金并且具有基本上垂直的侧壁，以及衬底上的与硅相邻的硅合金表面部分。

公开(公告)号：US20160163831A1

公开(公告)日：2016-06-09

申请号：US14676909

申请日：2015-04-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob

IPC: H01L29/66 ,  H01L21/762

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L29/7854

Abstract: A method includes forming a fin on a semiconductor substrate. An isolation structure is formed adjacent the fin. A silicon alloy material is formed on a portion of the fin extending above the isolation structure. A thermal process is performed to define a silicon alloy fin portion from the silicon alloy material and the fin and to define a first insulating layer separating the fin from the substrate.

Abstract translation: 一种方法包括在半导体衬底上形成翅片。 在翅片附近形成隔离结构。 在隔离结构上方延伸的翅片的一部分上形成硅合金材料。 执行热处理以从硅合金材料和翅片限定硅合金翅片部分并且限定将翅片与基底分离的第一绝缘层。

公开(公告)号：US09236479B2

公开(公告)日：2016-01-12

申请号：US14708405

申请日：2015-05-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Ajey Poovannummoottil Jacob

IPC: H01L27/092 ,  H01L27/12 ,  H01L29/66 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42372 ,  H01L29/66545 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/78603

Abstract: One method disclosed includes, among other things, removing a sacrificial gate structure to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to define a fin structure in a layer of semiconductor material using a patterned hard mask exposed within the replacement gate cavity as an etch mask and forming a replacement gate structure in the replacement gate cavity around at least a portion of the fin structure.

公开(公告)号：US09224865B2

公开(公告)日：2015-12-29

申请号：US13945627

申请日：2013-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Ajey Poovannummoottil Jacob

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/76224 ,  H01L29/66545 ,  H01L29/66795

Abstract: A FinFET has a structure including a semiconductor substrate, semiconductor fins and a gate spanning the fins. The fins each have a bottom region coupled to the substrate and a top active region. Between the bottom and top fin regions is a middle stack situated between a vertically elongated source and a vertically elongated drain. The stack includes a top channel region and a dielectric region immediately below the channel region, providing electrical isolation of the channel. The partial isolation structure can be used with both gate first and gate last fabrication processes.

Abstract translation: FinFET具有包括半导体衬底，半导体鳍片和横跨翅片的栅极的结构。 翅片各自具有连接到基底的底部区域和顶部活动区域。 位于底部和顶部翅片区域之间的是中间堆叠，位于垂直细长的源和垂直细长的排水管之间。 堆叠包括顶部通道区域和紧邻通道区域下方的电介质区域，提供通道的电隔离。 部分隔离结构可以与栅极第一和栅极末端制造工艺一起使用。

公开(公告)号：US09147748B1

公开(公告)日：2015-09-29

申请号：US14267555

申请日：2014-05-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Ajey Poovannummoottil Jacob ,  Andreas Knorr ,  Christopher Prindle

IPC: H01L21/283 ,  H01L29/66 ,  H01L21/311 ,  H01L21/285 ,  H01L29/45 ,  H01L29/51 ,  H01L29/49 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/41758 ,  H01L21/28518 ,  H01L21/31111 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/42372 ,  H01L29/45 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/78

Abstract: One illustrative method disclosed herein includes removing the sidewall spacers and a gate cap layer so as to thereby expose an upper surface and sidewalls of a sacrificial gate structure, forming an etch stop layer above source/drain regions of a device and on the sidewalls and upper surface of the sacrificial gate structure, forming a first layer of insulating material above the etch stop layer, removing the sacrificial gate structure so as to define a replacement gate cavity that is laterally defined by portions of the etch stop layer, forming a replacement gate structure in the replacement gate cavity, and forming a second gate cap layer above the replacement gate structure.

Abstract translation: 本文公开的一种示例性方法包括去除侧壁间隔件和栅极盖层，从而暴露牺牲栅极结构的上表面和侧壁，在器件的源极/漏极区域上方以及在侧壁和上部上形成蚀刻停止层 牺牲栅极结构的表面，在蚀刻停止层上方形成第一绝缘材料层，去除牺牲栅极结构，以便限定由蚀刻停止层的部分横向限定的替代栅极腔，形成替代栅极结构 并且在替换栅极结构上方形成第二栅极盖层。

公开(公告)号：US20150137237A1

公开(公告)日：2015-05-21

申请号：US14086199

申请日：2013-11-21

Applicant: Globalfoundries Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Murat K. Akarvardar

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/761 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/76224 ,  H01L29/0646 ,  H01L29/66795

Abstract: Approaches for isolating source and drain regions in an integrated circuit (IC) device (e.g., a fin field effect transistor (FinFET)) are provided. Specifically, the FinFET device comprises a gate structure formed over a finned substrate; an isolation oxide beneath an active fin channel of the gate structure; an embedded source and a drain (S/D) formed adjacent the gate structure and the isolation oxide; and an undoped epitaxial (epi) layer between the embedded S/D and the gate structure. The device may further include an epitaxial (epi) bottom region of the embedded S/D, wherein the epi bottom region is counter doped to a polarity of the embedded S/D, and a set of implanted regions implanted beneath the epi bottom region, wherein the set of implanted regions is doped and the epi bottom region is undoped. In one approach, the embedded S/D comprises P++ doped Silicon Germanium (SiGe) for a p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) and N++ Silicon Nitride (SiN) for a n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET).

Abstract translation: 提供了用于隔离集成电路（IC）器件（例如，鳍式场效应晶体管（FinFET））中的源极和漏极区域的方法。 具体地，FinFET器件包括形成在鳍式衬底上的栅极结构; 栅极结构的有源鳍式沟道下方的隔离氧化物; 形成在栅极结构和隔离氧化物附近的嵌入式源极和漏极（S / D）; 以及嵌入式S / D和栅极结构之间的未掺杂的外延（epi）层。 该器件可以进一步包括嵌入式S / D的外延（epi）底部区域，其中外延底部区域被反掺杂到嵌入式S / D的极性，以及一组注入在epi底部区域下方的注入区域， 其中所述一组注入区域是掺杂的，并且所述外延底部区域是未掺杂的。 在一种方法中，嵌入式S / D包括用于p沟道金属氧化物半导体场效应晶体管（PMOSFET）的P ++掺杂硅锗（SiGe）和用于n沟道金属氧化物半导体场效应晶体管的N ++氮化硅（SiN） 半导体场效应晶体管（NMOSFET）。

公开(公告)号：US09023705B1

公开(公告)日：2015-05-05

申请号：US14069868

申请日：2013-11-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Abhijeet Paul ,  Ajey Poovannummoottil Jacob ,  Min-hwa Chi

IPC: H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8232 ,  H01L29/423 ,  H01L27/088 ,  H01L27/105 ,  H01L29/08

CPC classification number: H01L29/66795 ,  H01L21/8232 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/105 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/42392 ,  H01L29/7848 ,  H01L29/785

Abstract: Disclosed are methods and devices that involve formation of alternating layers of different semiconductor materials in the channel region of FinFET devices. The methods involve forming such alternating layers of different semiconductor materials in a cavity formed above the substrate fin and thereafter forming a gate structure around the fin using gate first or gate last techniques.

Abstract translation: 公开了涉及在FinFET器件的沟道区域中形成不同半导体材料的交替层的方法和器件。 所述方法包括在形成在衬底鳍上方的空腔中形成不同半导体材料的这种交替层，然后使用栅极第一或栅极末端技术在鳍周围形成栅极结构。

公开(公告)号：US20150056781A1

公开(公告)日：2015-02-26

申请号：US13971937

申请日：2013-08-21

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Murat Kerem Akarvardar ,  Ajey Poovannummoottil Jacob

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L21/76264 ,  H01L21/02488 ,  H01L21/76224 ,  H01L29/66795

Abstract: Methods for fabricating integrated circuits and FinFET transistors on bulk substrates with active channel regions isolated from the substrate with an insulator are provided. In accordance with an exemplary embodiment, a method for fabricating an integrated circuit includes forming fin structures overlying a semiconductor substrate, wherein each fin structure includes a channel material and extends in a longitudinal direction from a first end to a second end. The method deposits an anchoring material over the fin structures. The method includes recessing the anchoring material to form trenches adjacent the fin structures, wherein the anchoring material remains in contact with the first end and the second end of each fin structure. Further, the method forms a void between the semiconductor substrate and the channel material of each fin structure with a gate length independent etching process, wherein the channel material of each fin structure is suspended over the semiconductor substrate.

Abstract translation: 提供了在具有与绝缘体与衬底隔离的有源沟道区的本体衬底上制造集成电路和FinFET晶体管的方法。 根据示例性实施例，一种用于制造集成电路的方法包括形成覆盖半导体衬底的鳍状结构，其中每个鳍结构包括沟道材料并且在纵向方向上从第一端延伸到第二端。 该方法将锚固材料沉积在翅片结构上。 该方法包括使锚固材料凹入以形成邻近翅片结构的沟槽，其中锚定材料保持与每个翅片结构的第一端和第二端接触。 此外，该方法在半导体衬底和每个鳍结构的沟道材料之间形成空隙，栅极长度独立蚀刻工艺，其中每个鳍结构的沟道材料悬置在半导体衬底上。

公开(公告)号：US20140361377A1

公开(公告)日：2014-12-11

申请号：US13914808

申请日：2013-06-11

Applicant: GLOBALFOUNDRIES Inc. ,  Renesas Electronics Corporation ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Steven John Bentley ,  Murat Kerem Akarvardar ,  Jody Alan Fronheiser ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Toshiharu Nagumo

IPC: H01L27/092 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Embodiments herein provide device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of high mobility channel fins is formed over the retrograde doped layer, each of the set of high mobility channel fins comprising a high mobility channel material (e.g., silicon or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of high mobility channel fins to prevent carrier spill-out to the high mobility channel fins.

Abstract translation: 本文的实施例提供了在互补金属氧化物鳍片场效应晶体管中的器件隔离。 具体地，半导体器件在衬底上形成有逆向掺杂层以最小化源极到漏极穿通泄漏。 一组高迁移率通道散热片形成在逆向掺杂层上，该组高迁移率通道散热片中的每一个包括高迁移率通道材料（例如硅或硅 - 锗）。 逆向掺杂层可以使用原位掺杂工艺或反掺杂剂逆向植入来形成。 该装置还可以包括位于逆向掺杂层和一组高迁移率通道翅片之间的碳衬垫，以防止载流子溢出到高迁移率通道翅片。